| /* | 
 |  * Copyright (c) 2017 Intel Corporation. | 
 |  * | 
 |  * SPDX-License-Identifier: Apache-2.0 | 
 |  */ | 
 |  | 
 | #include "skeleton.dtsi" | 
 | #include <dt-bindings/interrupt-controller/intel-mvic.h> | 
 | #include <dt-bindings/gpio/gpio.h> | 
 | #include <dt-bindings/i2c/i2c.h> | 
 |  | 
 | / { | 
 | 	cpus { | 
 | 		#address-cells = <1>; | 
 | 		#size-cells = <0>; | 
 |  | 
 | 		cpu@0 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "intel,quark"; | 
 | 			reg = <0>; | 
 | 		}; | 
 |  | 
 | 		intc: mvic { | 
 | 			compatible = "intel,mvic"; | 
 | 			interrupt-controller; | 
 | 			#interrupt-cells = <2>; | 
 | 		}; | 
 | 	}; | 
 |  | 
 | 	flash0: flash@180000 { | 
 | 		compatible = "soc-nv-flash"; | 
 | 		reg = <0x00180000 DT_FLASH_SIZE>; | 
 | 	}; | 
 |  | 
 | 	sram0: memory@280000 { | 
 | 		device_type = "memory"; | 
 | 		compatible = "mmio-sram"; | 
 | 		reg = <0x00280000 DT_SRAM_SIZE>; | 
 | 	}; | 
 |  | 
 |  | 
 | 	soc { | 
 | 		#address-cells = <1>; | 
 | 		#size-cells = <1>; | 
 | 		compatible = "simple-bus"; | 
 | 		ranges; | 
 |  | 
 | 		rtc: rtc@b0000400 { | 
 | 			compatible = "intel,qmsi-rtc"; | 
 | 			reg = <0xb0000400 0x400>; | 
 | 			clock-frequency = <32768>; | 
 | 			interrupts = <2 IRQ_TYPE_EDGE_RISING>; | 
 | 			interrupt-parent = <&intc>; | 
 | 			label = "RTC_0"; | 
 | 		}; | 
 |  | 
 | 		uart0: uart@b0002000 { | 
 | 			compatible = "intel,qmsi-uart"; | 
 | 			reg = <0xb0002000 0x400>; | 
 | 			label = "UART_0"; | 
 | 			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 |  | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		uart1: uart@b0002400 { | 
 | 			compatible = "intel,qmsi-uart"; | 
 | 			reg = <0xb0002400 0x400>; | 
 | 			label = "UART_1"; | 
 | 			interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 |  | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		gpio: gpio@b0000c00 { | 
 | 			compatible = "intel,qmsi-gpio"; | 
 | 			reg = <0xb0000c00 0x400>; | 
 | 			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 | 			label = "GPIO_0"; | 
 |  | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		i2c0: i2c@b0002800 { | 
 | 			compatible = "intel,qmsi-i2c"; | 
 | 			clock-frequency = <I2C_BITRATE_STANDARD>; | 
 | 			#address-cells = <1>; | 
 | 			#size-cells = <0>; | 
 | 			reg = <0xb0002800 0x400>; | 
 | 			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 | 			label = "I2C_0"; | 
 |  | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		adc0: adc@b0004000 { | 
 | 			compatible = "intel,quark-d2000-adc"; | 
 | 			#address-cells = <1>; | 
 | 			#size-cells = <0>; | 
 | 			reg = <0xB0004000 0x3F>; | 
 | 			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 | 			label = "ADC_0"; | 
 |  | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		spi0: spi@b0001000 { | 
 | 			compatible = "snps,designware-spi"; | 
 | 			#address-cells = <1>; | 
 | 			#size-cells = <0>; | 
 | 			reg = <0xb0001000 0x400>; | 
 | 			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			interrupt-parent = <&intc>; | 
 | 			label = "SPI_0"; | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		wdog0: watchdog@b0000000 { | 
 | 			compatible = "intel,qmsi-watchdog"; | 
 | 			#address-cells = <1>; | 
 | 			#size-cells = <0>; | 
 | 			reg = <0xb0000000 0x400>; | 
 | 			interrupts = <16 IRQ_TYPE_EDGE_RISING>; | 
 | 			interrupt-parent = <&intc>; | 
 |  | 
 | 			label = "WATCHDOG_0"; | 
 | 		}; | 
 | 	}; | 
 | }; |