blob: b0a6f254d3b122751e9d7f22615ef198a702a5b1 [file] [log] [blame]
/* SoC level DTS fixup file */
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_1_NAME ST_STM32_USART_40013800_LABEL
#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL
#define CONFIG_I2C_1_COMBINED_IRQ ST_STM32_I2C_V2_40005400_IRQ_COMBINED
#define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define CONFIG_I2C_2_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
#define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL
#define CONFIG_I2C_2_COMBINED_IRQ ST_STM32_I2C_V2_40005800_IRQ_COMBINED
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40007800_BASE_ADDRESS
#define CONFIG_I2C_3_COMBINED_IRQ_PRI ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY
#define CONFIG_I2C_3_NAME ST_STM32_I2C_V2_40007800_LABEL
#define CONFIG_I2C_3_COMBINED_IRQ ST_STM32_I2C_V2_40007800_IRQ_COMBINED
#define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0
#define CONFIG_USB_BASE_ADDRESS ST_STM32_USB_40005C00_BASE_ADDRESS
#define CONFIG_USB_IRQ ST_STM32_USB_40005C00_IRQ_USB
#define CONFIG_USB_IRQ_PRI ST_STM32_USB_40005C00_IRQ_USB_PRIORITY
#define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
#define CONFIG_USB_NUM_IN_ENDPOINTS ST_STM32_USB_40005C00_NUM_IN_ENDPOINTS
#define CONFIG_USB_NUM_OUT_ENDPOINTS ST_STM32_USB_40005C00_NUM_OUT_ENDPOINTS
#define CONFIG_USB_RAM_SIZE ST_STM32_USB_40005C00_RAM_SIZE
/* End of SoC Level DTS fixup file */