| # Microchip MEC172x MCU core series |
| |
| # Copyright (c) 2021 Microchip Technology Inc. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| choice |
| prompt "MEC172x Selection" |
| depends on SOC_SERIES_MEC172X |
| |
| config SOC_MEC172X_NSZ |
| bool "MEC172X_NSZ" |
| |
| endchoice |
| |
| config RTOS_TIMER |
| bool "MEC172x RTOS Timer(32KHz) as kernel timer" |
| |
| config SOC_MEC172X_PROC_CLK_DIV |
| int "PROC_CLK_DIV" |
| default 1 |
| range 1 48 |
| help |
| This divisor defines a ratio between processor clock (HCLK) |
| and main 96 MHz clock (MCK): |
| HCLK = MCK / PROC_CLK_DIV |
| Allowed divider values: 1, 3, 4, 16, and 48. |
| |
| config SOC_MEC172X_TEST_CLK_OUT |
| bool "Test clock out pin" |
| help |
| Enables a test clock out pin |
