| /* |
| * Copyright (c) 2017, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| |
| / { |
| cpus { |
| cpu@0 { |
| compatible = "arm,cortex-m4f"; |
| }; |
| cpu@1 { |
| compatible = "arm,cortex-m0+"; |
| }; |
| }; |
| |
| sram0:memory@20000000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 0x10000>; |
| }; |
| |
| sram1:memory@20010000 { |
| compatible = "mmio-sram"; |
| reg = <0x20010000 0x10000>; |
| }; |
| |
| sram2:memory@20020000 { |
| compatible = "mmio-sram"; |
| reg = <0x20020000 0x8000>; |
| }; |
| |
| sramx:memory@40000000{ |
| compatible = "mmio-sram"; |
| reg = <0x40000000 0x8000>; |
| }; |
| |
| soc { |
| |
| flash0:flash@0 { |
| reg = <0 0x40000>; |
| }; |
| |
| usart0:usart@40086000 { |
| compatible = "nxp,lpc-usart"; |
| reg = <0x40086000 0xE44>; |
| interrupts = <14 0>; |
| label = "USART_0"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |