| /* |
| * Copyright (c) 2022 Nordic Semiconductor |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| &pinctrl { |
| uart1_default: uart1_default { |
| group1 { |
| psels = <NRF_PSEL(UART_TX, 0, 24)>, |
| <NRF_PSEL(UART_RX, 0, 23)>; |
| }; |
| }; |
| |
| uart1_sleep: uart1_sleep { |
| group1 { |
| psels = <NRF_PSEL(UART_TX, 0, 24)>, |
| <NRF_PSEL(UART_RX, 0, 23)>; |
| low-power-enable; |
| }; |
| }; |
| |
| uart2_default: uart2_default { |
| group1 { |
| psels = <NRF_PSEL(UART_TX, 0, 4)>, |
| <NRF_PSEL(UART_RX, 0, 5)>; |
| }; |
| }; |
| |
| uart2_sleep: uart2_sleep { |
| group1 { |
| psels = <NRF_PSEL(UART_TX, 0, 4)>, |
| <NRF_PSEL(UART_RX, 0, 5)>; |
| low-power-enable; |
| }; |
| }; |
| |
| i2c2_default: i2c2_default { |
| group1 { |
| psels = <NRF_PSEL(TWIM_SDA, 0, 26)>, |
| <NRF_PSEL(TWIM_SCL, 0, 27)>; |
| }; |
| }; |
| |
| i2c2_sleep: i2c2_sleep { |
| group1 { |
| psels = <NRF_PSEL(TWIM_SDA, 0, 26)>, |
| <NRF_PSEL(TWIM_SCL, 0, 27)>; |
| low-power-enable; |
| }; |
| }; |
| |
| spi3_default: spi3_default { |
| group1 { |
| psels = <NRF_PSEL(SPIM_SCK, 0, 20)>, |
| <NRF_PSEL(SPIM_MOSI, 0, 21)>, |
| <NRF_PSEL(SPIM_MISO, 0, 22)>; |
| }; |
| }; |
| |
| spi3_sleep: spi3_sleep { |
| group1 { |
| psels = <NRF_PSEL(SPIM_SCK, 0, 20)>, |
| <NRF_PSEL(SPIM_MOSI, 0, 21)>, |
| <NRF_PSEL(SPIM_MISO, 0, 22)>; |
| low-power-enable; |
| }; |
| }; |
| |
| pwm0_default: pwm0_default { |
| group1 { |
| psels = <NRF_PSEL(PWM_OUT0, 0, 10)>, |
| <NRF_PSEL(PWM_OUT1, 0, 11)>, |
| <NRF_PSEL(PWM_OUT2, 0, 12)>; |
| nordic,invert; |
| }; |
| }; |
| |
| pwm0_sleep: pwm0_sleep { |
| group1 { |
| psels = <NRF_PSEL(PWM_OUT0, 0, 10)>, |
| <NRF_PSEL(PWM_OUT1, 0, 11)>, |
| <NRF_PSEL(PWM_OUT2, 0, 12)>; |
| low-power-enable; |
| }; |
| }; |
| |
| }; |