dts/arm/silabs/efr32bg27.dtsi

/*
 * Copyright (c) 2023 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "efr32bg2x.dtsi"
#include <dt-bindings/clock/silabs/xg27-clock.h>
#include <mem.h>

/ {
	clocks {
		hfxort: hfxort {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfxo>;
		};
		hfrcodpllrt: hfrcodpllrt {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hfrcodpll>;
		};
		eusart0clk: eusart0clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&em01grpaclk>;
		};
	};

	soc {
		clkin0: clkin0@5003c460 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			reg = <0x5003c460 0x4>;
			clock-frequency = <DT_FREQ_M(38)>;
		};
	};
};

&cmu {
	interrupts = <52 0>;
};

&hfxo {
	interrupts = <50 0>;
	interrupt-names = "hfxo";
};

&msc {
	flash0: flash@8000000 {
		compatible = "soc-nv-flash";
		write-block-size = <4>;
		erase-block-size = <8192>;
		reg = <0x08000000 DT_SIZE_K(768)>;
	};
};

&sram0 {
	reg = <0x20000000 DT_SIZE_K(64)>;
};

&gpio {
	interrupts = <30 2 31 2>;
	clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
};

&i2c0 {
	interrupts = <32 0>;
	clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
};

&i2c1 {
	interrupts = <33 0>;
	clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
};

&usart0 {
	interrupts = <16 0>, <17 0>;
	clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
};

&usart1 {
	interrupts = <18 0>, <19 0>;
	clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
};

&burtc0 {
	interrupts = <23 0>;
	clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
};

&rtcc0 {
	interrupts = <15 0>;
	interrupt-names = "rtcc";
	clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
};

&adc0 {
	interrupts = <54 0>;
	clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
};

&dcdc {
	interrupts = <8 0>;
};