dts/x86/intel/lakemont.dtsi

/*
 * Copyright (c) 2021 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "intel,lakemont", "intel,x86";
			d-cache-line-size = <64>;
			reg = <0>;
		};

	};

	intc: ioapic@fec00000  {
		compatible = "intel,ioapic";
		reg = <0xfec00000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	intc_loapic: loapic@fee00000  {
		compatible = "intel,loapic";
		reg = <0xfee00000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	/*
	 * Platforms with Lakemont SoC can have different hardware
	 * configurations. So RAM and peripherals need to be
	 * defined in the board configuration's DTS.
	 */
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
	};
};