soc/nxp/imxrt/Kconfig

# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_FAMILY_NXP_IMXRT
	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE

if SOC_FAMILY_NXP_IMXRT

# Source series Kconfig files first, so SOCs
# can override the defaults given here
rsource "*/Kconfig"

rsource "../common/Kconfig.flexspi_xip"

# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
# should be set elsewhere, since the determination of which SOC core
# requires the boot header is SOC specific.
config NXP_IMXRT_BOOT_HEADER
	bool "Boot header"
	default y
	depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX)
	help
	  Enable data structures required by the boot ROM to boot the
	  application from an external flash device.

if NXP_IMXRT_BOOT_HEADER

rsource "../common/Kconfig.rom_loader"

choice BOOT_DEVICE
	prompt "Boot device"
	default BOOT_FLEXSPI_NOR

config BOOT_FLEXSPI_NOR
	bool "FlexSPI serial NOR"
	depends on HAS_MCUX_FLEXSPI

config BOOT_FLEXSPI_NAND
	bool "FlexSPI serial NAND"
	depends on HAS_MCUX_FLEXSPI

config BOOT_SEMC_NOR
	bool "SEMC parallel NOR"
	depends on HAS_MCUX_SEMC

config BOOT_SEMC_NAND
	bool "SEMC parallel NAND"
	depends on HAS_MCUX_SEMC

endchoice # BOOT_DEVICE

config FLEXSPI_CONFIG_BLOCK_OFFSET
	hex "FlexSPI config block offset"
	default 0x0 if BOOT_FLEXSPI_NOR
	default 0x400
	help
	  FlexSPI configuration block consists of parameters regarding specific
	  flash devices including read command sequence, quad mode enablement
	  sequence (optional), etc. The boot ROM expects FlexSPI configuration
	  parameter to be presented in serial nor flash.

config IMAGE_VECTOR_TABLE_OFFSET
	hex "Image vector table offset"
	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
	default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
	help
	  The Image Vector Table (IVT) provides the boot ROM with pointers to
	  the application entry point and device configuration data. The boot
	  ROM requires a fixed IVT offset for each type of boot device.

config DEVICE_CONFIGURATION_DATA
	bool "Device configuration data"
	help
	  Device configuration data (DCD) provides a sequence of commands to
	  the boot ROM to initialize components such as an SDRAM. This is
	  useful if your application expects components like SDRAM to be
	  initialized at boot time.

config EXTERNAL_MEM_CONFIG_DATA
	bool "External Memory Configuration Data"
	depends on !DEVICE_CONFIGURATION_DATA
	help
	  External memory configuration data (XMDC) provides an alternative
	  configuration sequences which allows to intilialize the external memory
	  at the boot time. This sequence allows to configure
	  external memories (such as SDRAM) with more advanced option.
	  This is a new alternative boot header compared to DCD, and DCD must be disabled
	  in order to select this option.

config EXTERNAL_MEM_CONFIG_OFFSET
	hex "External memory configuration offset"
	depends on EXTERNAL_MEM_CONFIG_DATA
	default 0x800 if SOC_SERIES_IMXRT118X
	default 0x1040 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
	help
	  As specified by the boot ROM, the External Memory configuration data must be
	  placed in a specific address location to be pointed by the boot ROM.

endif # NXP_IMXRT_BOOT_HEADER

config NXP_IMX_EXTERNAL_SDRAM
	bool "Allow access to external SDRAM region"
	help
	  Enable access to external SDRAM region managed by the SEMC. This
	  setting should be enabled when the application uses SDRAM, or
	  an MPU region will be defined to disable cached access to the
	  SDRAM memory space.

config NXP_IMX_EXTERNAL_HYPERRAM
	bool "Allow access to external HYPERRAM region"
	help
	  Enable access to external HYPERRAM region managed by the FLEXSPI.
	  This setting should be enabled when the application uses HYPERRAM,
	  or an MPU region will be defined to disable cached access to the
	  HYPERRAM memory space.
config SECOND_CORE_MCUX
	bool "Dual core operation on the RT11xx series"
	depends on SOC_SERIES_IMXRT11XX
	help
	  Indicates the second core will be enabled, and the part will run
	  in dual core mode. Enables dual core operation on the RT11xx series,
	  by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
	  The M4 image will be loaded from flash into RAM based off a
	  generated header specifying the VMA and LMA of each memory section
	  to load

if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X

config PM_MCUX_GPC
	bool "MCUX general power controller driver"

config PM_MCUX_DCDC
	bool "MCUX dcdc converter module driver"

config PM_MCUX_PMU
	bool "MCUX power management unit driver"

config DCDC_VALUE
	hex "DCDC value for VDD_SOC"

config INIT_ARM_PLL
	bool "Initialize ARM PLL"

config INIT_VIDEO_PLL
	bool "Initialize Video PLL"

config INIT_ENET_PLL
	bool
	help
	  If y, the Ethernet PLL is initialized. Always enabled on e.g.
	  MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
	  for MIMXRT1021").

config INIT_SYS_PLL
	bool "Initialize System PLL"

endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X

endif # SOC_FAMILY_NXP_IMXRT