dts/xtensa/intel/intel_cavs15.dtsi

/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <xtensa/xtensa.dtsi>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx4";
			reg = <0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx4";
			reg = <1>;
		};
	};

	sram0: memory@be000000 {
		compatible = "mmio-sram";
		reg = <0xbe000000 DT_SIZE_K(512)>;
	};

	sram1: memory@be800000 {
		compatible = "mmio-sram";
		reg = <0xbe800000 DT_SIZE_K(128)>;
	};

	sysclk: system-clock {
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
		#clock-cells = <0>;
	};

	audioclk: audio-clock {
		compatible = "fixed-clock";
		clock-frequency = <24576000>;
		#clock-cells = <0>;
	};

	pllclk: pll-clock {
		compatible = "fixed-clock";
		clock-frequency = <96000000>;
		#clock-cells = <0>;
	};

	clkctl: clkctl {
		compatible = "intel,cavs-shim-clkctl";
		cavs-clkctl-clk-lpro = <0>;
		cavs-clkctl-clk-hpro = <2>;
		cavs-clkctl-freq-enc = <0x3 0x1 0x0>;
		cavs-clkctl-freq-default = <1>;
		cavs-clkctl-freq-lowest = <0>;
	};

	soc {
		shim: shim@1000 {
			compatible = "intel,cavs-shim";
			reg = <0x1000 0x100>;
		};

		win: win@1580 {
			compatible = "intel,cavs-win";
			reg = <0x1580 0x20>;
		};

		core_intc: core_intc@0 {
			compatible = "cdns,xtensa-core-intc";
			reg = <0x00 0x400>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		cavs_host_ipc: cavs_host_ipc@1180 {
			compatible = "intel,cavs-host-ipc";
			reg = <0x1180 0x30>;
			interrupts = <7 0 0>;
			interrupt-parent = <&cavs0>;
		};

		cavs0: cavs@1600  {
			compatible = "intel,cavs-intc";
			reg = <0x1600 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <6 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_0";
		};

		cavs1: cavs@1610  {
			compatible = "intel,cavs-intc";
			reg = <0x1610 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0xA 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_1";
		};

		cavs2: cavs@1620  {
			compatible = "intel,cavs-intc";
			reg = <0x1620 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0XD 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_2";
		};

		cavs3: cavs@1630  {
			compatible = "intel,cavs-intc";
			reg = <0x1630 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0x10 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_3";
		};

		idc: idc@1200 {
			compatible = "intel,cavs-idc";
			label = "CAVS_IDC";
			reg = <0x1200 0x80>;
			interrupts = <8 0 0>;
			interrupt-parent = <&cavs0>;
		};

		lpgpdma0: dma@c000 {
			compatible = "intel,cavs-gpdma";
			#dma-cells = <1>;
			reg = <0x0000c000 0x1000>;
			shim = <0x00000c00 0x080>;
			interrupts = <0x10 0 0>;
			interrupt-parent = <&cavs3>;
			label = "DMA_0";

			status = "okay";
		};

		lpgpdma1: dma@d000 {
			compatible = "intel,cavs-gpdma";
			#dma-cells = <1>;
			reg = <0x0000d000 0x1000>;
			shim = <0x00000c80 0x080>;
			interrupts = <0x0F 0 0>;
			interrupt-parent = <&cavs3>;
			label = "DMA_1";

			status = "okay";
		};

		hda_link_out: dma@2400 {
			compatible = "intel,cavs-hda-link-out";
			#dma-cells = <1>;
			reg = <0x00002400 0x40>;
			dma-channels = <6>;
			dma-buf-alignment = <128>;
			label = "HDA_LINK_OUT";

			status = "okay";
		};

		hda_link_in: dma@2600 {
			compatible = "intel,cavs-hda-link-in";
			#dma-cells = <1>;
			reg = <0x00002600 0x40>;
			dma-channels = <7>;
			dma-buf-alignment = <128>;
			label = "HDA_LINK_IN";

			status = "okay";
		};

		hda_host_out: dma@2800 {
			compatible = "intel,cavs-hda-host-out";
			#dma-cells = <1>;
			reg = <0x00002800 0x40>;
			dma-channels = <6>;
			dma-buf-alignment = <128>;
			label = "HDA_HOST_OUT";

			status = "okay";
		};

		hda_host_in: dma@2c00 {
			compatible = "intel,cavs-hda-host-in";
			#dma-cells = <1>;
			reg = <0x00002c00 0x40>;
			dma-channels = <7>;
			dma-buf-alignment = <128>;
			label = "HDA_HOST_IN";

			status = "okay";
		};

		ssp0: ssp@8000 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008000 0x200
			       0x00008E00 0x008>;
			interrupts = <0x01 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 2
				&lpgpdma0 3>;
			dma-names = "tx", "rx";
			label = "SSP_0";

			status = "okay";
		};

		ssp1: ssp@8200 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008200 0x200
			       0x00008E00 0x008>;
			interrupts = <0x01 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 4
				&lpgpdma0 5>;
			dma-names = "tx", "rx";
			label = "SSP_1";

			status = "okay";
		};

		ssp2: ssp@8400 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008400 0x200
			       0x00008E00 0x008>;
			interrupts = <0x02 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 6
				&lpgpdma0 7>;
			dma-names = "tx", "rx";
			label = "SSP_2";

			status = "okay";
		};

		ssp3: ssp@8600 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008600 0x200
			       0x00008E00 0x008>;
			interrupts = <0x03 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 8
				&lpgpdma0 9>;
			dma-names = "tx", "rx";
			label = "SSP_3";

			status = "okay";
		};

		ssp4: ssp@8800 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008800 0x200
			       0x00008E00 0x008>;
			interrupts = <0x03 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 10
				&lpgpdma0 11>;
			dma-names = "tx", "rx";
			label = "SSP_4";

			status = "okay";
		};

		ssp5: ssp@8a00 {
			compatible = "intel,ssp-dai";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00008A00 0x200
			       0x00008E00 0x008>;
			interrupts = <0x03 0 0>;
			interrupt-parent = <&cavs3>;
			dmas = <&lpgpdma0 12
				&lpgpdma0 13>;
			dma-names = "tx", "rx";
			label = "SSP_5";

			status = "okay";
		};
	};
};