| /* |
| * Copyright (c) 2019 Intel Corporation |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <xtensa/intel/intel_cavs.dtsi> |
| #include <mem.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx6"; |
| reg = <0>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx6"; |
| reg = <1>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx6"; |
| reg = <2>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx6"; |
| reg = <3>; |
| }; |
| }; |
| |
| sram0: memory@be000000 { |
| device_type = "memory"; |
| compatible = "mmio-sram"; |
| reg = <0xbe000000 DT_SIZE_K(1920)>; |
| }; |
| |
| sram1: memory@be800000 { |
| device_type = "memory"; |
| compatible = "mmio-sram"; |
| reg = <0xbe800000 DT_SIZE_K(64)>; |
| }; |
| |
| sysclk: system-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <38400000>; |
| #clock-cells = <0>; |
| }; |
| |
| audioclk: audio-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <24576000>; |
| #clock-cells = <0>; |
| }; |
| |
| pllclk: pll-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <96000000>; |
| #clock-cells = <0>; |
| }; |
| |
| clkctl: clkctl { |
| compatible = "intel,cavs-shim-clkctl"; |
| cavs-clkctl-clk-wovcro = <0>; |
| cavs-clkctl-clk-lpro = <1>; |
| cavs-clkctl-clk-hpro = <2>; |
| cavs-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>; |
| cavs-clkctl-freq-mask = <0x10 0x20000000 0x80000000>; |
| cavs-clkctl-freq-default = <2>; |
| cavs-clkctl-freq-lowest = <0>; |
| }; |
| |
| soc { |
| shim: shim@71f00 { |
| compatible = "intel,cavs-shim"; |
| reg = <0x71f00 0x100>; |
| }; |
| |
| win: win@71a00 { |
| compatible = "intel,cavs-win"; |
| reg = <0x71a00 0x20>; |
| }; |
| |
| sspbase: ssp_base@71c00 { |
| compatible = "intel,cavs-sspbase"; |
| reg = <0x71C00 0x100>; |
| }; |
| |
| l2lm: l2lm@71d00 { |
| compatible = "intel,cavs-l2lm"; |
| reg = <0x71d00 0x20>; |
| }; |
| |
| core_intc: core_intc@0 { |
| compatible = "cdns,xtensa-core-intc"; |
| reg = <0x00 0x400>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| cavs_host_ipc: cavs_host_ipc@71e00 { |
| compatible = "intel,cavs-host-ipc"; |
| reg = <0x71e00 0x30>; |
| interrupts = <7 0 0>; |
| interrupt-parent = <&cavs0>; |
| }; |
| |
| cavs0: cavs@78800 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x78800 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <6 0 0>; |
| interrupt-parent = <&core_intc>; |
| label = "CAVS_0"; |
| }; |
| |
| cavs1: cavs@78810 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x78810 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0xA 0 0>; |
| interrupt-parent = <&core_intc>; |
| label = "CAVS_1"; |
| }; |
| |
| cavs2: cavs@78820 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x78820 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0XD 0 0>; |
| interrupt-parent = <&core_intc>; |
| label = "CAVS_2"; |
| }; |
| |
| cavs3: cavs@78830 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x78830 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0x10 0 0>; |
| interrupt-parent = <&core_intc>; |
| label = "CAVS_3"; |
| }; |
| |
| idc: idc@1200 { |
| compatible = "intel,cavs-idc"; |
| label = "CAVS_IDC"; |
| reg = <0x1200 0x80>; |
| interrupts = <8 0 0>; |
| interrupt-parent = <&cavs0>; |
| }; |
| |
| tlb: tlb@3000 { |
| compatible = "intel,adsp-tlb"; |
| reg = <0x3000 0x1000>; |
| }; |
| |
| ssp0: ssp@77000 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077000 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x01 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 2 |
| &lpgpdma0 3>; |
| dma-names = "tx", "rx"; |
| label = "SSP_0"; |
| |
| status = "okay"; |
| }; |
| |
| ssp1: ssp@77200 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077200 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x01 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 4 |
| &lpgpdma0 5>; |
| dma-names = "tx", "rx"; |
| label = "SSP_1"; |
| |
| status = "okay"; |
| }; |
| |
| ssp2: ssp@77400 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077400 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x02 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 6 |
| &lpgpdma0 7>; |
| dma-names = "tx", "rx"; |
| label = "SSP_2"; |
| |
| status = "okay"; |
| }; |
| |
| ssp3: ssp@77600 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077600 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 8 |
| &lpgpdma0 9>; |
| dma-names = "tx", "rx"; |
| label = "SSP_3"; |
| |
| status = "okay"; |
| }; |
| |
| ssp4: ssp@77800 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077800 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 10 |
| &lpgpdma0 11>; |
| dma-names = "tx", "rx"; |
| label = "SSP_4"; |
| |
| status = "okay"; |
| }; |
| |
| ssp5: ssp@77a00 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00077A00 0x200 |
| 0x00078C00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs3>; |
| dmas = <&lpgpdma0 12 |
| &lpgpdma0 13>; |
| dma-names = "tx", "rx"; |
| label = "SSP_5"; |
| |
| status = "okay"; |
| }; |
| |
| alh0:alh@24400 { |
| compatible = "intel,alh-dai"; |
| reg = <0x00024400 0x00024600>; |
| label = "ALH_0"; |
| |
| status = "okay"; |
| }; |
| |
| alh1:alh@24400 { |
| compatible = "intel,alh-dai"; |
| reg = <0x00024400 0x00024600>; |
| label = "ALH_1"; |
| |
| status = "okay"; |
| }; |
| }; |
| }; |
