boards/arm/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi

/*
 * Copyright (c) 2022 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	uart0_default: uart0_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 29)>,
				<NRF_PSEL(UART_RX, 0, 30)>,
				<NRF_PSEL(UART_RTS, 0, 2)>,
				<NRF_PSEL(UART_CTS, 0, 28)>;
		};
	};

	uart0_sleep: uart0_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 29)>,
				<NRF_PSEL(UART_RX, 0, 30)>,
				<NRF_PSEL(UART_RTS, 0, 2)>,
				<NRF_PSEL(UART_CTS, 0, 28)>;
			low-power-enable;
		};
	};

	i2c0_default: i2c0_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
				<NRF_PSEL(TWIM_SCL, 0, 2)>;
		};
	};

	i2c0_sleep: i2c0_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
				<NRF_PSEL(TWIM_SCL, 0, 2)>;
			low-power-enable;
		};
	};

};