dts/x86/intel/intel_ish5_8.dtsi

/*
 * Copyright (c) 2023 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <intel/intel_ish5.dtsi>

&soc {
	interrupts = <
		8 IRQ_TYPE_FIXED_LEVEL_HIGH 1
		11 IRQ_TYPE_FIXED_LEVEL_HIGH 1
		12 IRQ_TYPE_FIXED_LEVEL_HIGH 1
	>;
	interrupt-names = "reset_prep", "pcidev", "pmu2ioapic";
};

&hpet {
	interrupts = <17 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;

	status = "okay";
};

&uart0 {
	interrupts = <28 IRQ_TYPE_LOWEST_EDGE_RISING 6>;

	status = "okay";
};

&uart1 {
	interrupts = <29 IRQ_TYPE_LOWEST_EDGE_RISING 6>;

	status = "disabled";
};

&uart2 {
	interrupts = <30 IRQ_TYPE_LOWEST_EDGE_RISING 6>;

	status = "disabled";
};

&i2c0 {
	interrupts = <18 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "okay";
};

&i2c1 {
	interrupts = <19 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "okay";
};

&i2c2 {
	interrupts = <20 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "disabled";
};

&gpio0 {
	interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "okay";
};

&spi0 {
	interrupts = <23 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "okay";
};

&spi1 {
	interrupts = <24 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "disabled";
};

&dma0 {
	interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;

	status = "disabled";
};