blob: feae5b3ccb966a78e546e51491b54c8c82d95565 [file] [log] [blame]
/*
* Copyright (c) 2017 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv6-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
aliases {
watchdog0 = &wdog;
};
chosen {
zephyr,flash-controller = &nvmctrl;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x8000>;
};
id: device_id@80a00c {
compatible = "atmel,sam0-id";
reg = <0x0080A00C 0x4>,
<0x0080A040 0x4>,
<0x0080A044 0x4>,
<0x0080A048 0x4>;
};
aliases {
port-a = &porta;
port-b = &portb;
adc-0 = &adc;
sercom-0 = &sercom0;
sercom-1 = &sercom1;
sercom-2 = &sercom2;
sercom-3 = &sercom3;
sercom-4 = &sercom4;
sercom-5 = &sercom5;
tc-4 = &tc4;
};
soc {
nvmctrl: nvmctrl@41004000 {
compatible = "atmel,sam0-nvmctrl";
reg = <0x41004000 0x22>;
interrupts = <5 0>;
lock-regions = <16>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0 0x40000>;
write-block-size = <4>;
};
};
pm: pm@40000400 {
compatible = "atmel,samd2x-pm";
reg = <0x40000400 0x400>;
interrupts = <0 0>;
#clock-cells = <2>;
};
gclk: gclk@40000c00 {
compatible = "atmel,samd2x-gclk";
reg = <0x40000c00 0x400>;
#clock-cells = <1>;
};
eic: eic@40001800 {
compatible = "atmel,sam0-eic";
reg = <0x40001800 0x1C>;
interrupts = <4 0>;
};
pinmux_a: pinmux@41004400 {
compatible = "atmel,sam0-pinmux";
reg = <0x41004400 0x80>;
};
pinmux_b: pinmux@41004480 {
compatible = "atmel,sam0-pinmux";
reg = <0x41004480 0x80>;
};
wdog: watchdog@40001000 {
compatible = "atmel,sam0-watchdog";
reg = <0x40001000 9>;
interrupts = <2 0>;
};
sercom0: sercom@42000800 {
compatible = "atmel,sam0-sercom";
reg = <0x42000800 0x40>;
status = "disabled";
};
sercom1: sercom@42000c00 {
compatible = "atmel,sam0-sercom";
reg = <0x42000c00 0x40>;
status = "disabled";
};
sercom2: sercom@42001000 {
compatible = "atmel,sam0-sercom";
reg = <0x42001000 0x40>;
status = "disabled";
};
sercom3: sercom@42001400 {
compatible = "atmel,sam0-sercom";
reg = <0x42001400 0x40>;
status = "disabled";
};
sercom4: sercom@42001800 {
compatible = "atmel,sam0-sercom";
reg = <0x42001800 0x40>;
status = "disabled";
};
sercom5: sercom@42001c00 {
compatible = "atmel,sam0-sercom";
reg = <0x42001c00 0x40>;
status = "disabled";
};
tc4: tc@42003000 {
compatible = "atmel,sam0-tc32";
reg = <0x42003000 0x20>;
};
pinctrl: pinctrl@41004400 {
compatible = "atmel,sam0-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41004400 0x41004400 0x100>;
porta: gpio@41004400 {
compatible = "atmel,sam0-gpio";
reg = <0x41004400 0x80>;
gpio-controller;
#gpio-cells = <2>;
#atmel,pin-cells = <2>;
};
portb: gpio@41004480 {
compatible = "atmel,sam0-gpio";
reg = <0x41004480 0x80>;
gpio-controller;
#gpio-cells = <2>;
#atmel,pin-cells = <2>;
};
};
rtc: rtc@40001400 {
compatible = "atmel,sam0-rtc";
reg = <0x40001400 0x1C>;
interrupts = <3 0>;
clock-generator = <0>;
status = "disabled";
};
adc: adc@42004000 {
compatible = "atmel,sam0-adc";
reg = <0x42004000 0x2B>;
/*
* 2.1 MHz max, so clock it with the
* 8 MHz GCLK / 4 = 2 MHz
*/
gclk = <3>;
prescaler = <4>;
#io-channel-cells = <1>;
};
dac0: dac@42004800 {
compatible = "atmel,sam0-dac";
status = "disabled";
reg = <0x42004800 0x10>;
#io-channel-cells = <0>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};