blob: 2bad616c81af94deae4a4115d8b916b2d545aedf [file] [log] [blame]
/*
* Copyright (c) 2021 Argentum Systems Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv6-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
aliases {
watchdog0 = &wdog;
};
chosen {
zephyr,flash-controller = &nvmctrl;
zephyr,entropy = &trng;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x8000>;
};
id: device_id@80a00c {
compatible = "atmel,sam0-id";
reg = <0x0080A00C 0x4>,
<0x0080A040 0x4>,
<0x0080A044 0x4>,
<0x0080A048 0x4>;
};
soc {
nvmctrl: nvmctrl@41004000 {
compatible = "atmel,sam0-nvmctrl";
reg = <0x41004000 0x22>;
interrupts = <4 0>;
lock-regions = <16>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0 0x40000>;
write-block-size = <4>;
};
};
pm: pm@40000400 {
compatible = "atmel,saml2x-pm";
reg = <0x40000400 0x400>;
interrupts = <0 0>;
#clock-cells = <2>;
};
mclk: mclk@40000400 {
compatible = "atmel,saml2x-mclk";
reg = <0x40000400 0x400>;
#clock-cells = <2>;
};
gclk: gclk@40001800 {
compatible = "atmel,saml2x-gclk";
reg = <0x40001800 0x400>;
#clock-cells = <1>;
};
dmac: dmac@44000400 {
compatible = "atmel,sam0-dmac";
reg = <0x44000400 0x400>;
interrupts = <5 0>;
#dma-cells = <2>;
};
eic: eic@40002400 {
compatible = "atmel,sam0-eic";
reg = <0x40002400 0x24>;
interrupts = <3 0>;
};
wdog: watchdog@40001c00 {
compatible = "atmel,sam0-watchdog";
reg = <0x40001c00 0x0c>;
interrupts = <1 0>;
};
sercom0: sercom@42000000 {
compatible = "atmel,sam0-sercom";
reg = <0x42000000 0x40>;
status = "disabled";
};
sercom1: sercom@42000400 {
compatible = "atmel,sam0-sercom";
reg = <0x42000400 0x40>;
status = "disabled";
};
sercom2: sercom@42000800 {
compatible = "atmel,sam0-sercom";
reg = <0x42000800 0x40>;
status = "disabled";
};
sercom3: sercom@42000c00 {
compatible = "atmel,sam0-sercom";
reg = <0x42000C00 0x40>;
status = "disabled";
};
sercom4: sercom@42001000 {
compatible = "atmel,sam0-sercom";
reg = <0x42001000 0x40>;
status = "disabled";
};
sercom5: sercom@43000400 {
compatible = "atmel,sam0-sercom";
reg = <0x43000400 0x40>;
status = "disabled";
};
tc4: tc@43000800 {
compatible = "atmel,sam0-tc32";
reg = <0x43000800 0x34>;
};
pinctrl: pinctrl@40002800 {
compatible = "atmel,sam0-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40002800 0x40002800 0x100>;
porta: gpio@40002800 {
compatible = "atmel,sam0-gpio";
reg = <0x40002800 0x80>;
gpio-controller;
#gpio-cells = <2>;
#atmel,pin-cells = <2>;
};
portb: gpio@40002880 {
compatible = "atmel,sam0-gpio";
reg = <0x40002880 0x80>;
gpio-controller;
#gpio-cells = <2>;
#atmel,pin-cells = <2>;
};
};
rtc: rtc@40002000 {
compatible = "atmel,sam0-rtc";
reg = <0x40002000 0x1c>;
interrupts = <2 0>;
clock-generator = <0>;
status = "disabled";
};
adc: adc@43000c00 {
compatible = "atmel,sam0-adc";
reg = <0x43000c00 0x30>;
/*
* 16 MHz max, so clock it with the
* 48 MHz DFLL / 2 / 2 = 12 MHz
*/
gclk = <3>;
prescaler = <2>;
#io-channel-cells = <1>;
};
dac: dac@42003000 {
compatible = "atmel,sam0-dac";
status = "disabled";
reg = <0x42003000 0x1a>;
#io-channel-cells = <0>;
};
trng: random@42003800 {
compatible = "atmel,sam-trng";
reg = <0x42003800 0x24>;
interrupts = <27 0>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};