boards/acrn/acrn/acrn.dts

/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <mem.h>

#define DT_DRAM_SIZE	DT_SIZE_K(8192)
#define DT_DRAM_BASE	0

#include <intel/atom.dtsi>

/ {
	model = "ACRN";
	compatible = "acrn";

	cpus {
		cpu@1 {
			device_type = "cpu";
			compatible = "intel,x86_64";
			d-cache-line-size = <64>;
			reg = <1>;
		};
	};

	aliases {
		uart-0 = &uart0;
		uart-1 = &uart1;
	};

	chosen {
		zephyr,sram = &dram0;
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
	};

	pcie0: pcie0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "pcie-controller";
		acpi-hid = "PNP0A08";
		ranges;
	};
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
};

&uart1 {
	status = "okay";
	current-speed = <115200>;
};

&cpu {
	compatible = "intel,x86_64";
};