arch/riscv32/soc/riscv-privilege/riscv32-qemu/dts.fixup

#define CONFIG_RISCV_RAM_BASE_ADDR		CONFIG_SRAM_BASE_ADDRESS

#define CONFIG_RISCV_ROM_BASE_ADDR		CONFIG_FLASH_BASE_ADDRESS

#define CONFIG_RISCV_ROM_SIZE			(CONFIG_FLASH_SIZE *1024)