/** | |
****************************************************************************** | |
* @file stm32f0xx_ll_cortex.h | |
* @author MCD Application Team | |
* @brief Header file of CORTEX LL module. | |
@verbatim | |
============================================================================== | |
##### How to use this driver ##### | |
============================================================================== | |
[..] | |
The LL CORTEX driver contains a set of generic APIs that can be | |
used by user: | |
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick | |
functions | |
(+) Low power mode configuration (SCB register of Cortex-MCU) | |
(+) API to access to MCU info (CPUID register) | |
@endverbatim | |
****************************************************************************** | |
* @attention | |
* | |
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> | |
* | |
* Redistribution and use in source and binary forms, with or without modification, | |
* are permitted provided that the following conditions are met: | |
* 1. Redistributions of source code must retain the above copyright notice, | |
* this list of conditions and the following disclaimer. | |
* 2. Redistributions in binary form must reproduce the above copyright notice, | |
* this list of conditions and the following disclaimer in the documentation | |
* and/or other materials provided with the distribution. | |
* 3. Neither the name of STMicroelectronics nor the names of its contributors | |
* may be used to endorse or promote products derived from this software | |
* without specific prior written permission. | |
* | |
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
* | |
****************************************************************************** | |
*/ | |
/* Define to prevent recursive inclusion -------------------------------------*/ | |
#ifndef __STM32F0xx_LL_CORTEX_H | |
#define __STM32F0xx_LL_CORTEX_H | |
#ifdef __cplusplus | |
extern "C" { | |
#endif | |
/* Includes ------------------------------------------------------------------*/ | |
#include "stm32f0xx.h" | |
/** @addtogroup STM32F0xx_LL_Driver | |
* @{ | |
*/ | |
/** @defgroup CORTEX_LL CORTEX | |
* @{ | |
*/ | |
/* Private types -------------------------------------------------------------*/ | |
/* Private variables ---------------------------------------------------------*/ | |
/* Private constants ---------------------------------------------------------*/ | |
/* Private macros ------------------------------------------------------------*/ | |
/* Exported types ------------------------------------------------------------*/ | |
/* Exported constants --------------------------------------------------------*/ | |
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants | |
* @{ | |
*/ | |
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source | |
* @{ | |
*/ | |
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ | |
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/* Exported macro ------------------------------------------------------------*/ | |
/* Exported functions --------------------------------------------------------*/ | |
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions | |
* @{ | |
*/ | |
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK | |
* @{ | |
*/ | |
/** | |
* @brief This function checks if the Systick counter flag is active or not. | |
* @note It can be used in timeout function on application side. | |
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag | |
* @retval State of bit (1 or 0). | |
*/ | |
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) | |
{ | |
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); | |
} | |
/** | |
* @brief Configures the SysTick clock source | |
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource | |
* @param Source This parameter can be one of the following values: | |
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 | |
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) | |
{ | |
if (Source == LL_SYSTICK_CLKSOURCE_HCLK) | |
{ | |
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
} | |
else | |
{ | |
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
} | |
} | |
/** | |
* @brief Get the SysTick clock source | |
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource | |
* @retval Returned value can be one of the following values: | |
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 | |
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK | |
*/ | |
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) | |
{ | |
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); | |
} | |
/** | |
* @brief Enable SysTick exception request | |
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_SYSTICK_EnableIT(void) | |
{ | |
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); | |
} | |
/** | |
* @brief Disable SysTick exception request | |
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_SYSTICK_DisableIT(void) | |
{ | |
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); | |
} | |
/** | |
* @brief Checks if the SYSTICK interrupt is enabled or disabled. | |
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT | |
* @retval State of bit (1 or 0). | |
*/ | |
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) | |
{ | |
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); | |
} | |
/** | |
* @} | |
*/ | |
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE | |
* @{ | |
*/ | |
/** | |
* @brief Processor uses sleep as its low power mode | |
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_EnableSleep(void) | |
{ | |
/* Clear SLEEPDEEP bit of Cortex System Control Register */ | |
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |
} | |
/** | |
* @brief Processor uses deep sleep as its low power mode | |
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) | |
{ | |
/* Set SLEEPDEEP bit of Cortex System Control Register */ | |
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |
} | |
/** | |
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. | |
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an | |
* empty main application. | |
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) | |
{ | |
/* Set SLEEPONEXIT bit of Cortex System Control Register */ | |
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |
} | |
/** | |
* @brief Do not sleep when returning to Thread mode. | |
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) | |
{ | |
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ | |
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |
} | |
/** | |
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the | |
* processor. | |
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) | |
{ | |
/* Set SEVEONPEND bit of Cortex System Control Register */ | |
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |
} | |
/** | |
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are | |
* excluded | |
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend | |
* @retval None | |
*/ | |
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) | |
{ | |
/* Clear SEVEONPEND bit of Cortex System Control Register */ | |
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |
} | |
/** | |
* @} | |
*/ | |
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO | |
* @{ | |
*/ | |
/** | |
* @brief Get Implementer code | |
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer | |
* @retval Value should be equal to 0x41 for ARM | |
*/ | |
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) | |
{ | |
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); | |
} | |
/** | |
* @brief Get Variant number (The r value in the rnpn product revision identifier) | |
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant | |
* @retval Value between 0 and 255 (0x0: revision 0) | |
*/ | |
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) | |
{ | |
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); | |
} | |
/** | |
* @brief Get Architecture number | |
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture | |
* @retval Value should be equal to 0xC for Cortex-M0 devices | |
*/ | |
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) | |
{ | |
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); | |
} | |
/** | |
* @brief Get Part number | |
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo | |
* @retval Value should be equal to 0xC20 for Cortex-M0 | |
*/ | |
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) | |
{ | |
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); | |
} | |
/** | |
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) | |
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision | |
* @retval Value between 0 and 255 (0x1: patch 1) | |
*/ | |
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) | |
{ | |
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); | |
} | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
#ifdef __cplusplus | |
} | |
#endif | |
#endif /* __STM32F0xx_LL_CORTEX_H */ | |
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |