soc/nxp/imxrt/imxrt11xx/Kconfig

# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_IMXRT11XX
	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
	select CPU_CORTEX_M_HAS_DWT
	select SOC_RESET_HOOK
	select ARM
	select CLOCK_CONTROL
	select HAS_MCUX_CACHE
	select HAS_MCUX
	select CPU_HAS_ARM_MPU
	select CPU_HAS_ICACHE if CPU_CORTEX_M7
	select CPU_HAS_DCACHE if CPU_CORTEX_M7
	select CPU_HAS_FPU
	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
	select HAS_SWO
	select HAS_PM

config SOC_MIMXRT1176_CM4
	select CPU_CORTEX_M4

config SOC_MIMXRT1176_CM7
	select CPU_CORTEX_M7

config SOC_MIMXRT1166_CM4
	select CPU_CORTEX_M4

config SOC_MIMXRT1166_CM7
	select CPU_CORTEX_M7

if SOC_SERIES_IMXRT11XX

config MCUX_CORE_SUFFIX
	default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7
	default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4

config BYPASS_LDO_LPSR
	default y
	bool "Bypass LDO lpsr"

config ADJUST_LDO
	default y
	bool "Adjust LDO setting"

config INIT_VIDEO_PLL
	default y

config SYS_PLL2_PFD0_DIV
	int "System PLL2 PFD0 divider"
	default 27
	range 13 35

config SYS_PLL2_PFD1_DIV
	int "System PLL2 PFD1 divider"
	default 16
	range 13 35

config SYS_PLL2_PFD2_DIV
	int "System PLL2 PFD2 divider"
	default 24
	range 13 35

config SYS_PLL2_PFD3_DIV
	int "System PLL2 PFD3 divider"
	default 32
	range 13 35

config SYS_PLL3_PFD0_DIV
	int "System PLL3 PFD0 divider"
	default 13
	range 13 35

config SYS_PLL3_PFD1_DIV
	int "System PLL3 PFD1 divider"
	default 17
	range 13 35

config SYS_PLL3_PFD2_DIV
	int "System PLL3 PFD2 divider"
	default 32
	range 13 35

config SYS_PLL3_PFD3_DIV
	int "System PLL3 PFD3 divider"
	default 22
	range 13 35

endif # SOC_SERIES_IMXRT11XX