drivers: adc: stm32f3 adc driver set common clock to HCLK
Set the synchronous clock mode to HCLK/1 (DIV1) or HCLK/2 (DIV2)
Both are valid common clock setting values.
The HCLK/1 (DIV1) is possible only if the ahb-prescaler = <1>
in the RCC_CFGR (see DTS).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
index 8fa5a31..3cdb80a 100644
--- a/drivers/adc/adc_stm32.c
+++ b/drivers/adc/adc_stm32.c
@@ -1158,8 +1158,7 @@
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32WLX)
LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
-#elif defined(STM32F3X_ADC_V1_1) || \
- defined(CONFIG_SOC_SERIES_STM32L4X) || \
+#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G0X) || \
@@ -1167,6 +1166,15 @@
defined(CONFIG_SOC_SERIES_STM32H7X)
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
LL_ADC_CLOCK_SYNC_PCLK_DIV4);
+#elif defined(STM32F3X_ADC_V1_1)
+ /*
+ * Set the synchronous clock mode to HCLK/1 (DIV1) or HCLK/2 (DIV2)
+ * Both are valid common clock setting values.
+ * The HCLK/1(DIV1) is possible only if
+ * the ahb-prescaler = <1> in the RCC_CFGR.
+ */
+ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
+ LL_ADC_CLOCK_SYNC_PCLK_DIV2);
#elif defined(CONFIG_SOC_SERIES_STM32L1X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
