dts: bindings: clocks stm32: Clock selection rewording and clarification
Change the wording about "alternate/optional" clock to "domain" clocks,
to better describe the feature and minimize confusion.
Additionally, provide more description about domain clocks and dual
domain functionality implemented in peripherals.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml
index 5803319..765278c 100644
--- a/dts/bindings/clock/st,stm32-rcc.yaml
+++ b/dts/bindings/clock/st,stm32-rcc.yaml
@@ -36,10 +36,13 @@
After the phandle referring to rcc node, the first index specifies the registers of
the bus controlling the peripheral and the second index specifies the bit used to
control the peripheral clock in that bus register.
+ The gated clock is required when accessing to the peripheral controller is needed
+ (generally for configuring the device). If dual clock domain is not used, it is
+ also used for peripheral operation.
- Specifying an alternate clock source:
+ Specifying a domain clock source:
- Specifying an alternate source clock could be done by adding a clock specifier to the
+ Specifying a domain source clock could be done by adding a clock specifier to the
clock property:
... {
...
@@ -47,10 +50,16 @@
<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
...
}
- In this example I2C1 device is assigned HSI as clock source.
- It is device driver's responsibility to querry and use clock source information in
+ In this example, I2C1 device is assigned HSI as domain clock source.
+ Domain clock is independent from the bus/gatted clock and allows access to the device's
+ register while the gated clock is off. As it doesn't feed the peripheral's controller, it
+ allows peripheral operation, but can't be used for peripheral configuration.
+ It is peripheral driver's responsibility to querry and use clock source information in
accordance with clock_control API specifications.
+ Since the peripheral subsystem rate is dictated by the clock used for peripheral
+ operation, same clock should be used in calls to `clock_control_get_rate()`
+
Note 1: No additional specifier means gating clock is also the clock source (ie
'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
cell to explicitly set it.
diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml
index 0c132c6..93a5266 100644
--- a/dts/bindings/clock/st,stm32h7-rcc.yaml
+++ b/dts/bindings/clock/st,stm32h7-rcc.yaml
@@ -26,25 +26,7 @@
d3ppre = <1>;
}
- Specifying a gated clock:
-
- To specify a gated clock, a peripheral should define a "clocks" property encoded
- in the following way:
- ... {
- ...
- clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
- ...
- }
- After the phandle referring to rcc node, the first index specifies the registers of
- the bus controlling the peripheral and the second index specifies the bit used to
- control the peripheral clock in that bus register.
-
- Note 1: No additional specifier means gating clock is also the clock source (ie
- 'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
- cell to explicitly set it.
- Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
- should be the one matching SoC reset state. Confere reference manual to check
- what is the reset value of the kernel clock source for each peripheral.
+ Confere st,stm32-rcc binding for information about domain clocks configuration.
compatible: "st,stm32h7-rcc"
