boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi

/*
 * Copyright 2024 NXP
 * SPDX-License-Identifier: Apache-2.0
 */

#include <nxp/nxp_imx/mimx9596avzxn-pinctrl.dtsi>

&pinctrl {
	lpi2c5_default: lpi2c5_default {
		group0 {
			pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>,
				<&iomuxc_gpio_io22_lpi2c_sda_lpi2c5_sda>;
			drive-open-drain;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
			input-enable;
		};
	};

	lpi2c7_default: lpi2c7_default {
		group0 {
			pinmux = <&iomuxc_gpio_io09_lpi2c_scl_lpi2c7_scl>,
				<&iomuxc_gpio_io08_lpi2c_sda_lpi2c7_sda>;
			drive-open-drain;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
			input-enable;
		};
	};

	lpuart1_default: lpuart1_default {
		group0 {
			pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
				<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
			bias-pull-up;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
		};
	};

	lpuart3_default: lpuart3_default {
		group0 {
			pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>,
				<&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>;
			bias-pull-up;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
		};
	};

	sai3_default: sai3_default {
		group0 {
			pinmux = <&iomuxc_gpio_io16_sai_tx_bclk_sai3_tx_bclk>,
				 <&iomuxc_gpio_io17_sai_mclk_sai3_mclk>,
				 <&iomuxc_gpio_io20_sai_rx_data_bit_sai3_rx_data_bit0>,
				 <&iomuxc_gpio_io21_sai_tx_data_bit_sai3_tx_data_bit0>,
				 <&iomuxc_gpio_io26_sai_tx_sync_sai3_tx_sync>;
			bias-pull-up;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
		};
	};

	tpm2_default: tpm2_default {
		group0 {
			pinmux = <&iomuxc_i2c2_scl_tpm_ch_tpm2_ch2>,
				<&iomuxc_i2c2_sda_tpm_ch_tpm2_ch3>;
			drive-open-drain;
			slew-rate = "slightly_fast";
			drive-strength = "x4";
			input-enable;
		};
	};
};