blob: 9a19e69aed7fc0f763bafc6fa1f0cda0ef72852a [file] [log] [blame]
/*
* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
* Copyright 2024, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nxp/nxp_lpc55S16_ns.dtsi>
#include "lpcxpresso55s16_common.dtsi"
/ {
model = "NXP LPCXpresso55S16 board";
compatible = "nxp,lpc55xxx", "nxp,lpc";
};
/*
* Default for this board is to allocate SRAM0-2 for data. But the
* application can have an application specific device tree to
* allocate the SRAMs differently.
*/
&sram0 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
zephyr_udc0: &usbhs {
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <5>;
tx-cal-45-dp-ohms = <10>;
tx-cal-45-dm-ohms = <10>;
};