/** | |
****************************************************************************** | |
* @file stm32f1xx_hal_rcc_ex.h | |
* @author MCD Application Team | |
* @version V1.1.1 | |
* @date 12-May-2017 | |
* @brief Header file of RCC HAL Extension module. | |
****************************************************************************** | |
* @attention | |
* | |
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> | |
* | |
* Redistribution and use in source and binary forms, with or without modification, | |
* are permitted provided that the following conditions are met: | |
* 1. Redistributions of source code must retain the above copyright notice, | |
* this list of conditions and the following disclaimer. | |
* 2. Redistributions in binary form must reproduce the above copyright notice, | |
* this list of conditions and the following disclaimer in the documentation | |
* and/or other materials provided with the distribution. | |
* 3. Neither the name of STMicroelectronics nor the names of its contributors | |
* may be used to endorse or promote products derived from this software | |
* without specific prior written permission. | |
* | |
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
* | |
****************************************************************************** | |
*/ | |
/* Define to prevent recursive inclusion -------------------------------------*/ | |
#ifndef __STM32F1xx_HAL_RCC_EX_H | |
#define __STM32F1xx_HAL_RCC_EX_H | |
#ifdef __cplusplus | |
extern "C" { | |
#endif | |
/* Includes ------------------------------------------------------------------*/ | |
#include "stm32f1xx_hal_def.h" | |
/** @addtogroup STM32F1xx_HAL_Driver | |
* @{ | |
*/ | |
/** @addtogroup RCCEx | |
* @{ | |
*/ | |
/** @addtogroup RCCEx_Private_Constants | |
* @{ | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/* Alias word address of PLLI2SON bit */ | |
#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos | |
#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) | |
/* Alias word address of PLL2ON bit */ | |
#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos | |
#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) | |
#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ | |
#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
#define CR_REG_INDEX ((uint8_t)1) | |
/** | |
* @} | |
*/ | |
/** @addtogroup RCCEx_Private_Macros | |
* @{ | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ | |
((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ | |
|| defined(STM32F100xE) | |
#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ | |
((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) | |
#else | |
#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) | |
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ | |
((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ | |
((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ | |
((__MUL__) == RCC_PLL_MUL6_5)) | |
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) | |
#else | |
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ | |
((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ | |
((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ | |
((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ | |
((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ | |
((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ | |
((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ | |
((__MUL__) == RCC_PLL_MUL16)) | |
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ | |
|| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) | |
#endif /* STM32F105xC || STM32F107xC*/ | |
#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ | |
((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) | |
#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) | |
#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) | |
#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ | |
((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ | |
((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ | |
((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ | |
((__MUL__) == RCC_PLLI2S_MUL20)) | |
#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ | |
((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) | |
#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ | |
((__PLL__) == RCC_PLL2_ON)) | |
#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ | |
((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ | |
((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ | |
((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ | |
((__MUL__) == RCC_PLL2_MUL20)) | |
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ | |
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) | |
#elif defined(STM32F103xE) || defined(STM32F103xG) | |
#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) | |
#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) | |
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ | |
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) | |
#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) | |
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ | |
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) | |
#else | |
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ | |
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ | |
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
/** | |
* @} | |
*/ | |
/* Exported types ------------------------------------------------------------*/ | |
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types | |
* @{ | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** | |
* @brief RCC PLL2 configuration structure definition | |
*/ | |
typedef struct | |
{ | |
uint32_t PLL2State; /*!< The new state of the PLL2. | |
This parameter can be a value of @ref RCCEx_PLL2_Config */ | |
uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock | |
This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. | |
This parameter can be a value of @ref RCCEx_Prediv2_Factor */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
} RCC_PLL2InitTypeDef; | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition | |
*/ | |
typedef struct | |
{ | |
uint32_t OscillatorType; /*!< The oscillators to be configured. | |
This parameter can be a value of @ref RCC_Oscillator_Type */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
uint32_t Prediv1Source; /*!< The Prediv1 source value. | |
This parameter can be a value of @ref RCCEx_Prediv1_Source */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
uint32_t HSEState; /*!< The new state of the HSE. | |
This parameter can be a value of @ref RCC_HSE_Config */ | |
uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) | |
This parameter can be a value of @ref RCCEx_Prediv1_Factor */ | |
uint32_t LSEState; /*!< The new state of the LSE. | |
This parameter can be a value of @ref RCC_LSE_Config */ | |
uint32_t HSIState; /*!< The new state of the HSI. | |
This parameter can be a value of @ref RCC_HSI_Config */ | |
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). | |
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ | |
uint32_t LSIState; /*!< The new state of the LSI. | |
This parameter can be a value of @ref RCC_LSI_Config */ | |
RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
} RCC_OscInitTypeDef; | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** | |
* @brief RCC PLLI2S configuration structure definition | |
*/ | |
typedef struct | |
{ | |
uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock | |
This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. | |
This parameter can be a value of @ref RCCEx_Prediv2_Factor */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
} RCC_PLLI2SInitTypeDef; | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @brief RCC extended clocks structure definition | |
*/ | |
typedef struct | |
{ | |
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. | |
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ | |
uint32_t RTCClockSelection; /*!< specifies the RTC clock source. | |
This parameter can be a value of @ref RCC_RTC_Clock_Source */ | |
uint32_t AdcClockSelection; /*!< ADC clock source | |
This parameter can be a value of @ref RCCEx_ADC_Prescaler */ | |
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
uint32_t I2s2ClockSelection; /*!< I2S2 clock source | |
This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ | |
uint32_t I2s3ClockSelection; /*!< I2S3 clock source | |
This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters | |
This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ | |
#endif /* STM32F105xC || STM32F107xC */ | |
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) | |
uint32_t UsbClockSelection; /*!< USB clock source | |
This parameter can be a value of @ref RCCEx_USB_Prescaler */ | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
} RCC_PeriphCLKInitTypeDef; | |
/** | |
* @} | |
*/ | |
/* Exported constants --------------------------------------------------------*/ | |
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants | |
* @{ | |
*/ | |
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection | |
* @{ | |
*/ | |
#define RCC_PERIPHCLK_RTC 0x00000001U | |
#define RCC_PERIPHCLK_ADC 0x00000002U | |
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
#define RCC_PERIPHCLK_I2S2 0x00000004U | |
#define RCC_PERIPHCLK_I2S3 0x00000008U | |
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) | |
#define RCC_PERIPHCLK_USB 0x00000010U | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler | |
* @{ | |
*/ | |
#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 | |
#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 | |
#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 | |
#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 | |
/** | |
* @} | |
*/ | |
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source | |
* @{ | |
*/ | |
#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source | |
* @{ | |
*/ | |
#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
/** @defgroup RCCEx_USB_Prescaler USB Prescaler | |
* @{ | |
*/ | |
#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE | |
#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U | |
/** | |
* @} | |
*/ | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_USB_Prescaler USB Prescaler | |
* @{ | |
*/ | |
#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE | |
#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor | |
* @{ | |
*/ | |
#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ | |
#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ | |
#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ | |
#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ | |
#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ | |
#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ | |
#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ | |
#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ | |
#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_Prediv1_Source Prediv1 Source | |
* @{ | |
*/ | |
#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE | |
#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor | |
* @{ | |
*/ | |
#define RCC_HSE_PREDIV_DIV1 0x00000000U | |
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ | |
|| defined(STM32F100xE) | |
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 | |
#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 | |
#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 | |
#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 | |
#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 | |
#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 | |
#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 | |
#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 | |
#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 | |
#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 | |
#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 | |
#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 | |
#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 | |
#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 | |
#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 | |
#else | |
#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE | |
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor | |
* @{ | |
*/ | |
#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ | |
#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ | |
#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ | |
#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ | |
#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ | |
#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ | |
#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ | |
#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ | |
#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ | |
#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ | |
#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ | |
#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ | |
#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ | |
#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ | |
#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ | |
#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_PLL2_Config PLL Config | |
* @{ | |
*/ | |
#define RCC_PLL2_NONE 0x00000000U | |
#define RCC_PLL2_OFF 0x00000001U | |
#define RCC_PLL2_ON 0x00000002U | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor | |
* @{ | |
*/ | |
#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ | |
#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ | |
#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ | |
#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ | |
#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ | |
#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ | |
#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ | |
#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ | |
#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor | |
* @{ | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#else | |
#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 | |
#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 | |
#endif /* STM32F105xC || STM32F107xC */ | |
#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 | |
#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 | |
#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 | |
#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 | |
#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 | |
#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 | |
#else | |
#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 | |
#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 | |
#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 | |
#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 | |
#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 | |
#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 | |
#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source | |
* @{ | |
*/ | |
#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) | |
#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) | |
#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) | |
#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) | |
#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) | |
#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) | |
#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) | |
#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) | |
#endif /* STM32F105xC || STM32F107xC*/ | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_Interrupt RCCEx Interrupt | |
* @{ | |
*/ | |
#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) | |
#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_Flag RCCEx Flag | |
* Elements values convention: 0XXYYYYYb | |
* - YYYYY : Flag position in the register | |
* - XX : Register index | |
* - 01: CR register | |
* @{ | |
*/ | |
/* Flags in the CR register */ | |
#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) | |
#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC*/ | |
/** | |
* @} | |
*/ | |
/* Exported macro ------------------------------------------------------------*/ | |
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros | |
* @{ | |
*/ | |
/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable | |
* @brief Enable or disable the AHB1 peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ | |
|| defined (STM32F100xE) | |
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined (STM32F100xE) | |
#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ | |
#if defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) | |
#endif /* STM32F103xE || STM32F103xG */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) | |
#endif /* STM32F105xC || STM32F107xC*/ | |
#if defined(STM32F107xC) | |
#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) | |
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) | |
#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) | |
/** | |
* @brief Enable ETHERNET clock. | |
*/ | |
#define __HAL_RCC_ETH_CLK_ENABLE() do { \ | |
__HAL_RCC_ETHMAC_CLK_ENABLE(); \ | |
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \ | |
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \ | |
} while(0U) | |
/** | |
* @brief Disable ETHERNET clock. | |
*/ | |
#define __HAL_RCC_ETH_CLK_DISABLE() do { \ | |
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \ | |
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \ | |
__HAL_RCC_ETHMAC_CLK_DISABLE(); \ | |
} while(0U) | |
#endif /* STM32F107xC*/ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status | |
* @brief Get the enable or disable status of the AHB1 peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ | |
|| defined (STM32F100xE) | |
#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) | |
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined (STM32F100xE) | |
#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) | |
#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ | |
#if defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) | |
#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) | |
#endif /* STM32F103xE || STM32F103xG */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) | |
#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) | |
#endif /* STM32F105xC || STM32F107xC*/ | |
#if defined(STM32F107xC) | |
#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) | |
#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) | |
#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) | |
#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) | |
#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) | |
#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) | |
#endif /* STM32F107xC*/ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable | |
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) | |
#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) | |
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ | |
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_USART3_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) | |
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) | |
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) | |
#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) | |
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_USB_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_UART4_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_UART5_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_DAC_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) | |
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) | |
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) | |
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) | |
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) | |
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) | |
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined (STM32F100xE) | |
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_DAC_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_CEC_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) | |
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) | |
#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) | |
#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#ifdef STM32F100xE | |
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_UART4_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_UART5_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) | |
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) | |
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) | |
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) | |
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) | |
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) | |
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) | |
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) | |
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) | |
#endif /* STM32F101xG || STM32F103xG*/ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status | |
* @brief Get the enable or disable status of the APB1 peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) | |
#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) | |
#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) | |
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ | |
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) | |
#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) | |
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) | |
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) | |
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) | |
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) | |
#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) | |
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) | |
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) | |
#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) | |
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) | |
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) | |
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) | |
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) | |
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) | |
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) | |
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) | |
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) | |
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) | |
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) | |
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) | |
#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) | |
#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined (STM32F100xE) | |
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) | |
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) | |
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) | |
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) | |
#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) | |
#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) | |
#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) | |
#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#ifdef STM32F100xE | |
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) | |
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) | |
#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) | |
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) | |
#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) | |
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) | |
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) | |
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) | |
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) | |
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) | |
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) | |
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) | |
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) | |
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) | |
#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) | |
#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) | |
#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) | |
#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) | |
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) | |
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) | |
#endif /* STM32F101xG || STM32F103xG*/ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable | |
* @brief Enable or disable the High Speed APB (APB2) peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) | |
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) | |
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) | |
#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) | |
#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ | |
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ | |
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) | |
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) | |
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ | |
#if defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) | |
#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) | |
#endif /* STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xE) | |
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) | |
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ | |
__IO uint32_t tmpreg; \ | |
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ | |
/* Delay after an RCC peripheral clock enabling */ \ | |
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ | |
UNUSED(tmpreg); \ | |
} while(0U) | |
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) | |
#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) | |
#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) | |
#endif /* STM32F101xG || STM32F103xG */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status | |
* @brief Get the enable or disable status of the APB2 peripheral clock. | |
* @note After reset, the peripheral clock (used for registers read/write access) | |
* is disabled and the application software has to enable this clock before | |
* using it. | |
* @{ | |
*/ | |
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) | |
#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) | |
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) | |
#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) | |
#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) | |
#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) | |
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) | |
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) | |
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ | |
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ | |
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) | |
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) | |
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) | |
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) | |
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) | |
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ | |
#if defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) | |
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) | |
#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) | |
#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) | |
#endif /* STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xE) | |
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) | |
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) | |
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) | |
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) | |
#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) | |
#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) | |
#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) | |
#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) | |
#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) | |
#endif /* STM32F101xG || STM32F103xG */ | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release | |
* @brief Force or release AHB peripheral reset. | |
* @{ | |
*/ | |
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) | |
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) | |
#if defined(STM32F107xC) | |
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) | |
#endif /* STM32F107xC */ | |
#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) | |
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) | |
#if defined(STM32F107xC) | |
#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) | |
#endif /* STM32F107xC */ | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset | |
* @brief Force or release APB1 peripheral reset. | |
* @{ | |
*/ | |
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) | |
#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) | |
#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) | |
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ | |
|| defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) | |
#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) | |
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) | |
#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) | |
#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) | |
#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) | |
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) | |
#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) | |
#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) | |
#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) | |
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) | |
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) | |
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) | |
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) | |
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) | |
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) | |
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) | |
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) | |
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) | |
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) | |
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) | |
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) | |
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F100xB) || defined (STM32F100xE) | |
#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) | |
#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) | |
#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) | |
#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) | |
#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) | |
#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) | |
#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) | |
#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#if defined (STM32F100xE) | |
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) | |
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) | |
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) | |
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) | |
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) | |
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) | |
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) | |
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) | |
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) | |
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) | |
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) | |
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) | |
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) | |
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) | |
#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) | |
#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) | |
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) | |
#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) | |
#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) | |
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) | |
#endif /* STM32F101xG || STM32F103xG */ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset | |
* @brief Force or release APB2 peripheral reset. | |
* @{ | |
*/ | |
#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ | |
|| defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) | |
#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) | |
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xB) || defined(STM32F100xE) | |
#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) | |
#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) | |
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) | |
#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) | |
#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) | |
#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) | |
#endif /* STM32F100xB || STM32F100xE */ | |
#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ | |
|| defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ | |
|| defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ | |
|| defined(STM32F107xC) | |
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) | |
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) | |
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ | |
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ | |
|| defined(STM32F103xG) | |
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) | |
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) | |
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) | |
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) | |
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ | |
#if defined(STM32F103xE) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) | |
#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) | |
#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) | |
#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) | |
#endif /* STM32F103xE || STM32F103xG */ | |
#if defined(STM32F100xE) | |
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) | |
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) | |
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) | |
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) | |
#endif /* STM32F100xE */ | |
#if defined(STM32F101xG) || defined(STM32F103xG) | |
#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) | |
#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) | |
#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) | |
#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) | |
#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) | |
#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) | |
#endif /* STM32F101xG || STM32F103xG*/ | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_HSE_Configuration HSE Configuration | |
* @{ | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ | |
|| defined(STM32F100xE) | |
/** | |
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. | |
* @note Predivision factor can not be changed if PLL is used as system clock | |
* In this case, you have to select another source of the system clock, disable the PLL and | |
* then change the HSE predivision factor. | |
* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. | |
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. | |
*/ | |
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) | |
#else | |
/** | |
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. | |
* @note Predivision factor can not be changed if PLL is used as system clock | |
* In this case, you have to select another source of the system clock, disable the PLL and | |
* then change the HSE predivision factor. | |
* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. | |
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. | |
*/ | |
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ | |
MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) | |
#endif /* STM32F105xC || STM32F107xC */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ | |
|| defined(STM32F100xE) | |
/** | |
* @brief Macro to get prediv1 factor for PLL. | |
*/ | |
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) | |
#else | |
/** | |
* @brief Macro to get prediv1 factor for PLL. | |
*/ | |
#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) | |
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration | |
* @{ | |
*/ | |
/** @brief Macros to enable the main PLLI2S. | |
* @note After enabling the main PLLI2S, the application software should wait on | |
* PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can | |
* be used as system clock source. | |
* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. | |
*/ | |
#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) | |
/** @brief Macros to disable the main PLLI2S. | |
* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. | |
*/ | |
#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) | |
/** @brief macros to configure the main PLLI2S multiplication factor. | |
* @note This function must be used only when the main PLLI2S is disabled. | |
* | |
* @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 | |
* @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 | |
* @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 | |
* @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 | |
* @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 | |
* @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 | |
* @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 | |
* @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 | |
* @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 | |
* | |
*/ | |
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ | |
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration | |
* @brief Macros to configure clock source of different peripherals. | |
* @{ | |
*/ | |
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ | |
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) | |
/** @brief Macro to configure the USB clock. | |
* @param __USBCLKSOURCE__ specifies the USB clock source. | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock | |
*/ | |
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ | |
MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) | |
/** @brief Macro to get the USB clock (USBCLK). | |
* @retval The clock source can be one of the following values: | |
* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock | |
*/ | |
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) | |
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @brief Macro to configure the USB OTSclock. | |
* @param __USBCLKSOURCE__ specifies the USB clock source. | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock | |
*/ | |
#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ | |
MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) | |
/** @brief Macro to get the USB clock (USBCLK). | |
* @retval The clock source can be one of the following values: | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock | |
* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock | |
*/ | |
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). | |
* @param __ADCCLKSOURCE__ specifies the ADC clock source. | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock | |
*/ | |
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ | |
MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) | |
/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). | |
* @retval The clock source can be one of the following values: | |
* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock | |
* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock | |
*/ | |
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @addtogroup RCCEx_HSE_Configuration | |
* @{ | |
*/ | |
/** | |
* @brief Macro to configure the PLL2 & PLLI2S Predivision factor. | |
* @note Predivision factor can not be changed if PLL2 is used indirectly as system clock | |
* In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and | |
* then change the PREDIV2 factor. | |
* @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. | |
* This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. | |
*/ | |
#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ | |
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) | |
/** | |
* @brief Macro to get prediv2 factor for PLL2 & PLL3. | |
*/ | |
#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) | |
/** | |
* @} | |
*/ | |
/** @addtogroup RCCEx_PLLI2S_Configuration | |
* @{ | |
*/ | |
/** @brief Macros to enable the main PLL2. | |
* @note After enabling the main PLL2, the application software should wait on | |
* PLL2RDY flag to be set indicating that PLL2 clock is stable and can | |
* be used as system clock source. | |
* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. | |
*/ | |
#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) | |
/** @brief Macros to disable the main PLL2. | |
* @note The main PLL2 can not be disabled if it is used indirectly as system clock source | |
* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. | |
*/ | |
#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) | |
/** @brief macros to configure the main PLL2 multiplication factor. | |
* @note This function must be used only when the main PLL2 is disabled. | |
* | |
* @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 | |
* @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 | |
* @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 | |
* @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 | |
* @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 | |
* @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 | |
* @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 | |
* @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 | |
* @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 | |
* | |
*/ | |
#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ | |
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) | |
/** | |
* @} | |
*/ | |
/** @defgroup RCCEx_I2S_Configuration I2S Configuration | |
* @brief Macros to configure clock source of I2S peripherals. | |
* @{ | |
*/ | |
/** @brief Macro to configure the I2S2 clock. | |
* @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry | |
* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry | |
*/ | |
#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ | |
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) | |
/** @brief Macro to get the I2S2 clock (I2S2CLK). | |
* @retval The clock source can be one of the following values: | |
* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry | |
* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry | |
*/ | |
#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) | |
/** @brief Macro to configure the I2S3 clock. | |
* @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. | |
* This parameter can be one of the following values: | |
* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry | |
* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry | |
*/ | |
#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ | |
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) | |
/** @brief Macro to get the I2S3 clock (I2S3CLK). | |
* @retval The clock source can be one of the following values: | |
* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry | |
* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry | |
*/ | |
#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
/* Exported functions --------------------------------------------------------*/ | |
/** @addtogroup RCCEx_Exported_Functions | |
* @{ | |
*/ | |
/** @addtogroup RCCEx_Exported_Functions_Group1 | |
* @{ | |
*/ | |
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); | |
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); | |
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); | |
/** | |
* @} | |
*/ | |
#if defined(STM32F105xC) || defined(STM32F107xC) | |
/** @addtogroup RCCEx_Exported_Functions_Group2 | |
* @{ | |
*/ | |
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); | |
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); | |
/** | |
* @} | |
*/ | |
/** @addtogroup RCCEx_Exported_Functions_Group3 | |
* @{ | |
*/ | |
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); | |
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); | |
/** | |
* @} | |
*/ | |
#endif /* STM32F105xC || STM32F107xC */ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
/** | |
* @} | |
*/ | |
#ifdef __cplusplus | |
} | |
#endif | |
#endif /* __STM32F1xx_HAL_RCC_EX_H */ | |
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ | |