dts/bindings/rng/st,stm32-rng.yaml

# Copyright (c) 2020, Linaro Limited
# SPDX-License-Identifier: Apache-2.0

description: STM32 Random Number Generator

compatible: "st,stm32-rng"

include: base.yaml

properties:
  reg:
    required: true

  clocks:
    required: true
    description: |
         Specifies the clock line to be enabled in clock controller as well as
         the clock domain used, for instance:
                   <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
         A correctly configured domain clock is required to allow the integrated low
         sampling clock detection mechanism to behave properly.
         In the provided example, MSI should be configured to provide 48Mhz clock.

  nist-config:
    type: int
    description: |
         This property is used to configure the RNG_CR for the NIST certification
         The validation conditions are following the refMan
         to certify NIST SP800-90B. RNG clock source must be 48MHz.
         This config is valid with some STM32 families
         and when Conditioning Soft Reset (RNG_CR_CONDRST bit) exists.
         The value is directly mapped from the RNG configuration (A) table.
         The Health Register (health-test-config property) must correspond
         to this table configuration.
         On the stm32U5, the ARDIS bit7 is also written.

  health-test-magic:
    type: int
    description: |
         Magic Number to be written to Health Test Configuration Register (HTCR)
         prior to real configuration, if any.

  health-test-config:
    type: int
    description: |
         Heath Test Configuration, necessary to have proper RNG behavior,
         when available.