| # NXP S32K3XX MCU series |
| |
| # Copyright 2023-2024 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_SERIES_S32K3 |
| select ARM |
| select CPU_CORTEX_M7 |
| select HAS_NXP_S32_HAL |
| select CPU_HAS_FPU |
| select CPU_HAS_ARM_MPU |
| select CPU_HAS_ICACHE |
| select CPU_HAS_DCACHE |
| select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS |
| select PLATFORM_SPECIFIC_INIT if XIP |
| select USE_DT_CODE_PARTITION if XIP |
| select CLOCK_CONTROL |
| select HAS_MCUX |
| select HAS_MCUX_LPUART |
| select HAS_MCUX_FLEXCAN |
| select HAS_MCUX_LPI2C |
| select HAS_MCUX_LPSPI |
| select HAS_MCUX_CACHE |
| |
| if SOC_SERIES_S32K3 |
| |
| config IVT_HEADER_OFFSET |
| hex |
| depends on XIP |
| default $(dt_node_reg_addr_hex,$(dt_nodelabel_path,ivt_header)) |
| help |
| The offset address from flash base address for ivt header |
| |
| config IVT_HEADER_SIZE |
| hex |
| depends on XIP |
| default $(dt_node_reg_size_hex,$(dt_nodelabel_path,ivt_header)) |
| help |
| Size of ivt header region |
| |
| config NXP_S32_PMC_LMEN |
| bool "Last Mile regulator" |
| default y if CLOCK_CONTROL |
| help |
| Enables the Last Mile regulator, which regulates an external 1.5V |
| voltage on V15 down to the core and logic supply (V11 power domain), |
| which is typically 1.1V. |
| When enabling PLL as system clock, the PMC last mile regulator should |
| be enabled. |
| |
| config NXP_S32_PMC_LMBCTLEN |
| bool "External BCTL regulator for V15" |
| depends on NXP_S32_PMC_LMEN |
| help |
| This option must be selected if an external BJT between VDD_HV_A and |
| V15 is used on the PCB. The base of this BJT must be connected to the |
| VRC_CTRL pin and is controlled by the PMC to regulate a voltage of |
| 1.5V on V15 pin. |
| |
| endif # SOC_SERIES_S32K3 |
