dts/arm/adi/max32/max32657-pinctrl.dtsi

/*
 * Copyright (c) 2024-2025 Analog Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>

&pinctrl {
	/omit-if-no-ref/ i3c_scl_p0_0: i3c_scl_p0_0 {
		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
	};

	/omit-if-no-ref/ i3c_sda_p0_1: i3c_sda_p0_1 {
		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
	};

	/omit-if-no-ref/ spi0_mosi_p0_2: spi0_mosi_p0_2 {
		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
	};

	/omit-if-no-ref/ spi0_ss0_p0_3: spi0_ss0_p0_3 {
		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
	};

	/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
	};

	/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
	};

	/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
	};

	/omit-if-no-ref/ spi0_ss1_p0_7: spi0_ss1_p0_7 {
		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
	};

	/omit-if-no-ref/ spi0_ss2_p0_8: spi0_ss2_p0_8 {
		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
	};

	/omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 {
		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
	};

	/omit-if-no-ref/ sqwout_p0_13: sqwout_p0_13 {
		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
	};

	/omit-if-no-ref/ tmr0a_p0_0: tmr0a_p0_0 {
		pinmux = <MAX32_PINMUX(0, 0, AF2)>;
	};

	/omit-if-no-ref/ tmr1a_p0_1: tmr1a_p0_1 {
		pinmux = <MAX32_PINMUX(0, 1, AF2)>;
	};

	/omit-if-no-ref/ tmr3a_p0_2: tmr3a_p0_2 {
		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
	};

	/omit-if-no-ref/ tmr4a_p0_3: tmr4a_p0_3 {
		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
	};

	/omit-if-no-ref/ tmr5a_p0_4: tmr5a_p0_4 {
		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
	};

	/omit-if-no-ref/ tmr0b_p0_5: tmr0b_p0_5 {
		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
	};

	/omit-if-no-ref/ tmr4b_p0_6: tmr4b_p0_6 {
		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
	};

	/omit-if-no-ref/ tmr3b_p0_7: tmr3b_p0_7 {
		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
	};

	/omit-if-no-ref/ i3c_pur_p0_8: i3c_pur_p0_8 {
		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
	};

	/omit-if-no-ref/ tmr1b_p0_9: tmr1b_p0_9 {
		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
	};

	/omit-if-no-ref/ tmr2a_p0_10: tmr2a_p0_10 {
		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
	};

	/omit-if-no-ref/ tmr5b_p0_11: tmr5b_p0_11 {
		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
	};
};

/* Low power modes pin state,
 * user shall set related configurations like:
 * pullup/pulldown, out/in...
 * incase of their needs on the their target board
 */
&pinctrl {
	/omit-if-no-ref/ i3c_scl_p0_0_sleep: i3c_scl_p0_0_sleep {
		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ i3c_sda_p0_1_sleep: i3c_sda_p0_1_sleep {
		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_mosi_p0_2_sleep: spi0_mosi_p0_2_sleep {
		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_ss0_p0_3_sleep: spi0_ss0_p0_3_sleep {
		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_miso_p0_4_sleep: spi0_miso_p0_4_sleep {
		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ uart0_rx_p0_5_sleep: uart0_rx_p0_5_sleep {
		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_sck_p0_6_sleep: spi0_sck_p0_6_sleep {
		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_ss1_p0_7_sleep: spi0_ss1_p0_7_sleep {
		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ spi0_ss2_p0_8_sleep: spi0_ss2_p0_8_sleep {
		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ uart0_tx_p0_9_sleep: uart0_tx_p0_9_sleep {
		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ sqwout_p0_13_sleep: sqwout_p0_13_sleep {
		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr0a_p0_0_sleep: tmr0a_p0_0_sleep {
		pinmux = <MAX32_PINMUX(0, 0, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr1a_p0_1_sleep: tmr1a_p0_1_sleep {
		pinmux = <MAX32_PINMUX(0, 1, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr3a_p0_2_sleep: tmr3a_p0_2_sleep {
		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr4a_p0_3_sleep: tmr4a_p0_3_sleep {
		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr5a_p0_4_sleep: tmr5a_p0_4_sleep {
		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr0b_p0_5_sleep: tmr0b_p0_5_sleep {
		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr4b_p0_6_sleep: tmr4b_p0_6_sleep {
		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr3b_p0_7_sleep: tmr3b_p0_7_sleep {
		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ i3c_pur_p0_8_sleep: i3c_pur_p0_8_sleep {
		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr1b_p0_9_sleep: tmr1b_p0_9_sleep {
		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr2a_p0_10_sleep: tmr2a_p0_10_sleep {
		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
		low-power-enable;
	};

	/omit-if-no-ref/ tmr5b_p0_11_sleep: tmr5b_p0_11_sleep {
		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
		low-power-enable;
	};
};