soc: riscv: riscv-privilege: opentitan: Fix PLIC interrupts
1. Fixes the number of interrupts in OpenTitan by default. This should
be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
including interrupt 0.
2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
PLIC interrupt on IRQ 11.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
diff --git a/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
index 9d3bd05..c9e7f83 100644
--- a/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
+++ b/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
@@ -24,7 +24,10 @@
config 2ND_LVL_ISR_TBL_OFFSET
default 32
+config 2ND_LVL_INTR_00_OFFSET
+ default 11
+
config NUM_IRQS
- default 216
+ default 217
endif # SOC_SERIES_RISCV_OPENTITAN