commit e6075541abea29336ccdda68aeaf913cadf13a3b
author Tyler Ng <tkng@rivosinc.com> Tue Apr 25 13:53:22 2023 -0700
committer Anas Nashif <anas.nashif@intel.com> Fri May 26 09:45:25 2023 -0400
tree 964462fd07447fee41d41575456242d1ae343ecd
parent ae350a9c773ab527eb1fa93eeb45bef7beca9a5a

soc: riscv: riscv-privilege: opentitan: Fix PLIC interrupts

1. Fixes the number of interrupts in OpenTitan by default. This should
   be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
   including interrupt 0.

2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
   PLIC interrupt on IRQ 11.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>

soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series

diff --git a/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
index 9d3bd05..c9e7f83 100644
--- a/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
+++ b/soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
@@ -24,7 +24,10 @@
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 32
 
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
 config NUM_IRQS
-	default 216
+	default 217
 
 endif # SOC_SERIES_RISCV_OPENTITAN