blob: c3382bca86f2b03a7308df15a9dda2804e1c14cf [file] [log] [blame]
/*
* Copyright (c) 2024 Pratik Farkase <pratik.farkase@wsisweden.com>
* Copyright (c) 2024 Sigma Connectivity WSI AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "jh7110-clk.dtsi"
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <freq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "starfive,jh7110";
model = "starfive,jh7110";
cpus {
#address-cells = <1>;
#size-cells = <0>;
S7_0: cpu@0 {
compatible = "sifive,s7", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac_zicsr_zifencei";
status = "okay";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
U74_1: cpu@1 {
compatible = "sifive,u74", "riscv";
device_type = "cpu";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0x1>;
riscv,isa = "rv64imafdcg";
tlb-spilt;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
U74_2: cpu@2 {
compatible = "sifive,u74", "riscv";
device_type = "cpu";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0x2>;
riscv,isa = "rv64imafdcg";
tlb-split;
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
U74_3: cpu@3 {
compatible = "sifive,u74", "riscv";
device_type = "cpu";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0x3>;
riscv,isa = "rv64imafdcg";
tlb-split;
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
U74_4: cpu@4 {
compatible = "sifive,u74", "riscv";
device_type = "cpu";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <40>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <40>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0x4>;
riscv,isa = "rv64imafdcg";
tlb-split;
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
l2lim: memory@8000000 {
device_type = "memory";
reg = <0x0 0x8000000 0x0 0x200000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
compatible = "starfive,jh7110", "simple-bus";
ranges;
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
};
ccache: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
interrupt-parent = <&plic>;
interrupts = <1>, <3>, <4>, <2>;
reg = <0x0 0x2010000 0x0 0x4000>;
};
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
reg = <0x0 0x0c000000 0x0 0x04000000>;
riscv,max-priority = <7>;
riscv,ndev = <52>;
};
uart0: serial@10000000 {
compatible = "ns16550", "snps,dw-apb-uart";
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
clock-frequency = <100000000>;
current-speed = <115200>;
interrupt-parent = <&plic>;
interrupts = <32 1>;
reg = <0x0 0x10000000 0x0 0x10000>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@10010000 {
compatible = "ns16550", "snps,dw-apb-uart";
clocks = <&uartclk>, <&apb2clk>;
clock-names = "baudclk", "apb_pclk";
clock-frequency = <100000000>;
current-speed = <115200>;
interrupt-parent = <&plic>;
interrupts = <33 1>;
reg = <0x0 0x10010000 0x0 0x10000>;
reg-shift = <2>;
status = "disabled";
};
};
};