boards: arm: Add NXP mimxrt1050_evk
Adds support for the NXP MIMXRT1050-EVK board, an entry-level
development board for the new mimxrt1052 Cortex-M7 SoC.
Adds pinmuxing, dts, documentation, and jlink debug support for the new
board. Note that pinmuxing uses the mcux pinmux driver directly rather
than the Zephyr pinmux interface. The mimxrt1052 SoC has complicated
pinmuxing that may require changing the Zephyr pinmux interface to
support, so for now let's use the mcux driver directly.
We are also not yet configuring the external flash, therefore a debugger
is required to load code to the internal sram. The on-board OpenSDA
circuit with jlink firmware is sufficient, and the 'make debug' build
target is supported.
Samples tested include: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
diff --git a/boards/arm/mimxrt1050_evk/CMakeLists.txt b/boards/arm/mimxrt1050_evk/CMakeLists.txt
new file mode 100644
index 0000000..c164107
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/CMakeLists.txt
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+zephyr_library_sources(pinmux.c)
diff --git a/boards/arm/mimxrt1050_evk/Kconfig.board b/boards/arm/mimxrt1050_evk/Kconfig.board
new file mode 100644
index 0000000..15191e2
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/Kconfig.board
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MIMXRT1050_EVK
+ bool "NXP MIMXRT1050-EVK"
+ depends on SOC_SERIES_IMX_RT
+ select SOC_PART_NUMBER_MIMXRT1052DVL6A
diff --git a/boards/arm/mimxrt1050_evk/Kconfig.defconfig b/boards/arm/mimxrt1050_evk/Kconfig.defconfig
new file mode 100644
index 0000000..e40f784
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/Kconfig.defconfig
@@ -0,0 +1,39 @@
+# Kconfig - MIMXRT1050-EVK board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MIMXRT1050_EVK
+
+config BOARD
+ default mimxrt1050_evk
+
+if GPIO_MCUX_IGPIO
+
+config GPIO_MCUX_IGPIO_1
+ def_bool y
+
+config GPIO_MCUX_IGPIO_2
+ def_bool n
+
+config GPIO_MCUX_IGPIO_3
+ def_bool n
+
+config GPIO_MCUX_IGPIO_4
+ def_bool n
+
+config GPIO_MCUX_IGPIO_5
+ def_bool y
+
+endif # GPIO_MCUX_IGPIO
+
+if UART_MCUX_LPUART
+
+config UART_MCUX_LPUART_1
+ def_bool y
+
+endif # UART_MCUX_LPUART
+
+endif # BOARD_MIMXRT1050_EVK
diff --git a/boards/arm/mimxrt1050_evk/board.cmake b/boards/arm/mimxrt1050_evk/board.cmake
new file mode 100644
index 0000000..3408461
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/board.cmake
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set_ifndef(OPENSDA_FW jlink)
+
+if(OPENSDA_FW STREQUAL jlink)
+ set_ifndef(DEBUG_SCRIPT jlink.sh)
+endif()
+
+set_property(GLOBAL APPEND PROPERTY FLASH_SCRIPT_ENV_VARS
+ JLINK_DEVICE=Cortex-M7
+ )
diff --git a/boards/arm/mimxrt1050_evk/board.h b/boards/arm/mimxrt1050_evk/board.h
new file mode 100644
index 0000000..bfd9e0f
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/board.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#define LED0_GPIO_PORT CONFIG_MCUX_IGPIO_1_NAME
+#define LED0_GPIO_PIN 9
+
+#define SW0_GPIO_NAME CONFIG_MCUX_IGPIO_5_NAME
+#define SW0_GPIO_PIN 0
+
+#endif /* __INC_BOARD_H */
diff --git a/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg b/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg
new file mode 100644
index 0000000..622b8dd
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg
Binary files differ
diff --git a/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.rst b/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.rst
new file mode 100644
index 0000000..5e2d947
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.rst
@@ -0,0 +1,197 @@
+.. _mimxrt1050_evk:
+
+NXP MIMXRT1050-EVK
+##################
+
+Overview
+********
+
+The i.MX RT1050 is a new processor family featuring NXP's advanced
+implementation of the ARM Cortex-M7 Core. It provides high CPU performance and
+real-time response. The i.MX RT1050 provides various memory interfaces,
+including SDRAM, Raw NAND FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a
+wide range of other interfaces for connecting peripherals, such as WLAN,
+Bluetooth™, GPS, displays, and camera sensors. As with other i.MX processors,
+i.MX RT1050 also has rich audio and video features, including LCD display,
+basic 2D graphics, camera interface, SPDIF, and I2S audio interface.
+
+.. image:: mimxrt1050_evk.jpg
+ :width: 720px
+ :align: center
+ :alt: MIMXRT1050-EVK
+
+Hardware
+********
+
+- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM)
+
+- Memory
+
+ - 256 KB SDRAM
+ - 64 Mbit QSPI Flash
+ - 512 Mbit Hyper Flash
+
+- Display
+
+ - LCD connector
+
+- Ethernet
+
+ - 10/100 Mbit/s Ethernet PHY
+
+- USB
+
+ - USB 2.0 OTG connector
+ - USB 2.0 host connector
+
+- Audio
+
+ - 3.5 mm audio stereo headphone jack
+ - Board-mounted microphone
+ - Left and right speaker out connectors
+
+- Power
+
+ - 5 V DC jack
+
+- Debug
+
+ - JTAG 20-pin connector
+ - OpenSDA with DAPLink
+
+- Sensor
+
+ - FXOS8700CQ 6-axis e-compass
+ - CMOS camera sensor interface
+
+- Expansion port
+
+ - Arduino interface
+
+- CAN bus connector
+
+For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see
+these references:
+
+- `i.MX RT1050 Website`_
+- `i.MX RT1050 Datasheet`_
+- `i.MX RT1050 Reference Manual`_
+- `MIMXRT1050-EVK Website`_
+- `MIMXRT1050-EVK User Guide`_
+- `MIMXRT1050-EVK Schematics`_
+
+Supported Features
+==================
+
+The mimxrt1050_evk board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component |
++===========+============+=====================================+
+| NVIC | on-chip | nested vector interrupt controller |
++-----------+------------+-------------------------------------+
+| SYSTICK | on-chip | systick |
++-----------+------------+-------------------------------------+
+| GPIO | on-chip | gpio |
++-----------+------------+-------------------------------------+
+| UART | on-chip | serial port-polling; |
+| | | serial port-interrupt |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+
+ ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig``
+
+Other hardware features are not currently supported by the port.
+
+Connections and IOs
+===================
+
+The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
+
++---------------+-----------------+---------------------------+
+| Name | Function | Usage |
++===============+=================+===========================+
+| GPIO_AD_B0_09 | GPIO | LED |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_12 | LPUART1_TX | UART Console |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
++---------------+-----------------+---------------------------+
+| WAKEUP | GPIO | SW0 |
++---------------+-----------------+---------------------------+
+
+System Clock
+============
+
+The MIMXRT1050 SoC is configured to use the 24 MHz external oscillator on the
+board with the on-chip PLL to generate a 528 MHz system clock.
+
+Serial Port
+===========
+
+The MIMXRT1050 SoC has eight UARTs. One is configured for the console and the
+remaining are not used.
+
+Programming and Debugging
+*************************
+
+The MIMXRT1050-EVK includes the :ref:`nxp_opensda` serial and debug adapter
+built into the board to provide debugging, flash programming, and serial
+communication over USB.
+
+To use the Segger J-Link tools with OpenSDA, follow the instructions in the
+:ref:`nxp_opensda_jlink` page using the `Segger J-Link OpenSDA V2.1 Firmware`_.
+The Segger J-Link tools are the default for this board, therefore it is not
+necessary to set ``OPENSDA_FW=jlink`` explicitly when you invoke ``make
+debug``.
+
+The pyOCD tools do not yet support this SoC.
+
+Flashing
+========
+
+The Segger J-Link firmware does not support command line flashing, therefore
+the ``make flash`` build target is not supported.
+
+Debugging
+=========
+
+This example uses the :ref:`hello_world` sample with the
+:ref:`nxp_opensda_jlink` tools. Use the ``make debug`` build target to build
+your Zephyr application, invoke the J-Link GDB server, attach a GDB client, and
+program your Zephyr application to flash. The following commands will do all
+that, and leave you at a gdb prompt.
+
+.. code-block:: console
+
+ $ cd <zephyr_root_path>
+ $ . zephyr-env.sh
+ $ cd samples/hello_world/
+ $ make BOARD=mimxrt1050_evk debug
+
+
+.. _MIMXRT1050-EVK Website:
+ https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
+
+.. _MIMXRT1050-EVK User Guide:
+ https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf
+
+.. _MIMXRT1050-EVK Schematics:
+ https://www.nxp.com/webapp/Download?colCode=MIMXRT1050-EVK-DESIGNFILES
+
+.. _i.MX RT1050 Website:
+ https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050
+
+.. _i.MX RT1050 Datasheet:
+ https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf
+
+.. _i.MX RT1050 Reference Manual:
+ https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf
+
+.. _DAPLink FRDM-K64F Firmware:
+ http://www.nxp.com/assets/downloads/data/en/ide-debug-compile-build-tools/OpenSDAv2.2_DAPLink_frdmk64f_rev0242.zip
+
+.. _Segger J-Link OpenSDA V2.1 Firmware:
+ https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin
diff --git a/boards/arm/mimxrt1050_evk/dts.fixup b/boards/arm/mimxrt1050_evk/dts.fixup
new file mode 100644
index 0000000..50cfee2
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/dts.fixup
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_MCUX_CCM_BASE_ADDRESS NXP_IMX_CCM_400FC000_BASE_ADDRESS_0
+#define CONFIG_MCUX_CCM_NAME NXP_IMX_CCM_400FC000_LABEL
+
+#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS NXP_IMX_GPIO_401B8000_BASE_ADDRESS_0
+#define CONFIG_MCUX_IGPIO_1_NAME NXP_IMX_GPIO_401B8000_LABEL
+#define CONFIG_MCUX_IGPIO_1_IRQ_0 NXP_IMX_GPIO_401B8000_IRQ_0
+#define CONFIG_MCUX_IGPIO_1_IRQ_0_PRI NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY
+#define CONFIG_MCUX_IGPIO_1_IRQ_1 NXP_IMX_GPIO_401B8000_IRQ_1
+#define CONFIG_MCUX_IGPIO_1_IRQ_1_PRI NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY
+
+#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS NXP_IMX_GPIO_400C0000_BASE_ADDRESS_0
+#define CONFIG_MCUX_IGPIO_5_NAME NXP_IMX_GPIO_400C0000_LABEL
+#define CONFIG_MCUX_IGPIO_5_IRQ_0 NXP_IMX_GPIO_400C0000_IRQ_0
+#define CONFIG_MCUX_IGPIO_5_IRQ_0_PRI NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY
+#define CONFIG_MCUX_IGPIO_5_IRQ_1 NXP_IMX_GPIO_400C0000_IRQ_1
+#define CONFIG_MCUX_IGPIO_5_IRQ_1_PRI NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY
+
+#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS NXP_KINETIS_LPUART_40184000_BASE_ADDRESS_0
+#define CONFIG_UART_MCUX_LPUART_1_NAME NXP_KINETIS_LPUART_40184000_LABEL
+#define CONFIG_UART_MCUX_LPUART_1_IRQ NXP_KINETIS_LPUART_40184000_IRQ_0
+#define CONFIG_UART_MCUX_LPUART_1_IRQ_PRI NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY
+#define CONFIG_UART_MCUX_LPUART_1_BAUD_RATE NXP_KINETIS_LPUART_40184000_CURRENT_SPEED
+#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME NXP_IMX_CCM_400FC000_LABEL
+#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CCM_CLK_NAME_0
diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
new file mode 100644
index 0000000..c6bb694
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt.dtsi>
+
+/ {
+ model = "NXP MIMXRT1050-EVK board";
+ compatible = "nxp,mimxrt1052";
+
+ aliases {
+ gpio_1= &gpio1;
+ gpio_2= &gpio2;
+ gpio_3= &gpio3;
+ gpio_4= &gpio4;
+ gpio_5= &gpio5;
+ uart_1 = &uart1;
+ };
+
+ chosen {
+ zephyr,flash = &itcm0;
+ zephyr,sram = &dtcm0;
+ zephyr,console = &uart1;
+ };
+};
+
+&uart1 {
+ status = "ok";
+ current-speed = <115200>;
+};
diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml
new file mode 100644
index 0000000..5d5d898
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1050_evk
+name: NXP MIMXRT1050-EVK
+type: mcu
+arch: arm
+toolchain:
+ - zephyr
+ - gccarmemb
diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig
new file mode 100644
index 0000000..2dc8a66
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM=y
+CONFIG_SOC_MIMXRT1052=y
+CONFIG_SOC_SERIES_IMX_RT=y
+CONFIG_BOARD_MIMXRT1050_EVK=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=528000000
+CONFIG_OSC_EXTERNAL=y
diff --git a/boards/arm/mimxrt1050_evk/pinmux.c b/boards/arm/mimxrt1050_evk/pinmux.c
new file mode 100644
index 0000000..bc47a0b
--- /dev/null
+++ b/boards/arm/mimxrt1050_evk/pinmux.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <fsl_iomuxc.h>
+
+static int mimxrt1050_evk_init(struct device *dev)
+{
+ ARG_UNUSED(dev);
+
+ CLOCK_EnableClock(kCLOCK_Iomuxc);
+ CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+ /* LED */
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
+
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
+ IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+ /* SW0 */
+ IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
+
+#ifdef CONFIG_UART_MCUX_LPUART_1
+ /* LPUART1 TX/RX */
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
+ IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
+
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
+ IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+ IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
+ IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+ IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+ IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+#endif
+
+ return 0;
+}
+
+SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
