| /* |
| * Copyright (c) 2023 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/h5/stm32h562.dtsi> |
| |
| / { |
| soc { |
| compatible = "st,stm32h563", "st,stm32h5", "simple-bus"; |
| |
| sdmmc2: sdmmc@46008c00 { |
| compatible = "st,stm32-sdmmc"; |
| reg = <0x46008c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 12)>, |
| <&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>; |
| resets = <&rctl STM32_RESET(AHB4, 12U)>; |
| interrupts = <102 0>; |
| status = "disabled"; |
| }; |
| |
| ethernet@40028000 { |
| reg = <0x40028000 0x8000>; |
| compatible = "st,stm32-ethernet-controller"; |
| clock-names = "stm-eth"; |
| clocks = <&rcc STM32_CLOCK(AHB1, 19)>; |
| |
| mac: ethernet { |
| compatible = "st,stm32h7-ethernet", "st,stm32-ethernet"; |
| interrupts = <106 0>; |
| clock-names = "mac-clk-tx", "mac-clk-rx"; |
| clocks = <&rcc STM32_CLOCK(AHB1, 20)>, |
| <&rcc STM32_CLOCK(AHB1, 21)>; |
| status = "disabled"; |
| }; |
| |
| mdio: mdio { |
| compatible = "st,stm32-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| fdcan2: can@4000a800 { |
| compatible = "st,stm32-fdcan"; |
| reg = <0x4000a800 0x400>, <0x4000ac00 0x6a0>; |
| reg-names = "m_can", "message_ram"; |
| interrupts = <109 0>, <110 0>; |
| interrupt-names = "int0", "int1"; |
| /* common clock FDCAN 1 & 2 */ |
| clocks = <&rcc STM32_CLOCK(APB1_2, 9)>, |
| <&rcc STM32_SRC_HSE FDCAN_SEL(0)>; |
| bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
