| /* |
| * Copyright (C) 2025 Savoir-faire Linux, Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <freq.h> |
| #include <mem.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/clock/stm32mp2_clock.h> |
| #include <zephyr/dt-bindings/reset/stm32mp2_reset.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| }; |
| }; |
| |
| ddr_code: memory0@80100000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "DDR_CODE"; |
| }; |
| |
| ddr_sys: memory1@80a00000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "DDR_SYS"; |
| }; |
| |
| soc { |
| rcc: rcc@44200000 { |
| compatible = "st,stm32mp2-rcc"; |
| clocks-controller; |
| #clock-cells = <2>; |
| reg = <0x44200000 DT_SIZE_K(64)>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti2: interrupt-controller@46230000 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x46230000 DT_SIZE_K(1)>; |
| num-lines = <77>; |
| interrupts = <17 0>, <18 0>, <19 0>, <20 0>, |
| <21 0>, <22 0>, <23 0>, <24 0>, |
| <25 0>, <26 0>, <27 0>, <28 0>, |
| <29 0>, <30 0>, <31 0>, <32 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5", "line6", "line7", |
| "line8", "line9", "line10", "line11", |
| "line12", "line13", "line14", "line15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 1>, <6 1>, <7 1>, |
| <8 1>, <9 1>, <10 1>, <11 1>, |
| <12 1>, <13 1>, <14 1>, <15 1>; |
| }; |
| |
| pinctrl: pin-controller@44240000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x44240000 0xb0000>; |
| |
| gpioa: gpio@44240000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44240000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpiob: gpio@44250000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44250000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioc: gpio@44260000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44260000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpiod: gpio@44270000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44270000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioe: gpio@44280000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44280000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpiof: gpio@44290000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x44290000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpiog: gpio@442a0000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x442a0000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioh: gpio@442b0000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x442b0000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioi: gpio@442c0000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x442c0000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioj: gpio@442d0000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x442d0000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpiok: gpio@442e0000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x442e0000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| |
| gpioz: gpio@46200000 { |
| compatible = "st,stm32mp2-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x46200000 DT_SIZE_K(1)>; |
| status = "disabled"; |
| }; |
| }; |
| |
| spi1: spi@40230000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x40230000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI1, STM32_CLK)>; |
| interrupts = <112 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@400b0000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x400b0000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI2, STM32_CLK)>; |
| interrupts = <113 0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@400c0000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x400c0000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI3, STM32_CLK)>; |
| interrupts = <125 0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@40240000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x40240000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI4, STM32_CLK)>; |
| interrupts = <152 0>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@40280000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x40280000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI5, STM32_CLK)>; |
| interrupts = <153 0>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@40350000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x40350000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI6, STM32_CLK)>; |
| interrupts = <154 0>; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@40360000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| reg = <0x40360000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(SPI7, STM32_CLK)>; |
| interrupts = <155 0>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40330000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40330000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(USART1, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(USART1, STM32_RST)>; |
| interrupts = <114 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@400e0000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x400e0000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(USART2, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(USART2, STM32_RST)>; |
| interrupts = <115 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@400f0000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x400f0000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(USART3, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(USART3, STM32_RST)>; |
| interrupts = <116 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40100000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40100000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(UART4, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(UART4, STM32_RST)>; |
| interrupts = <126 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40110000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40110000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(UART5, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(UART5, STM32_RST)>; |
| interrupts = <127 0>; |
| status = "disabled"; |
| }; |
| |
| usart6: serial@40220000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40220000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(USART6, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(USART6, STM32_RST)>; |
| interrupts = <136 0>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@40370000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40370000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(UART7, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(UART7, STM32_RST)>; |
| interrupts = <148 0>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@40380000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40380000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(UART8, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(UART8, STM32_RST)>; |
| interrupts = <149 0>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@402c0000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x402c0000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(UART9, STM32_CLK)>; |
| resets = <&rctl STM32_RESET(UART9, STM32_RST)>; |
| interrupts = <150 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40120000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40120000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C1, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <108 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40130000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40130000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C2, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <110 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40140000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40140000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C3, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <137 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@40150000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40150000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C4, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <168 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@40160000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40160000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C5, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <181 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@40170000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40170000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C6, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <208 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@40180000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40180000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C7, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <210 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c8: i2c@46040000 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x46040000 DT_SIZE_K(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(I2C8, STM32_CLK)>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <212 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| iwdg: iwdg4: watchdog@44040000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x44040000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(IWDG4, STM32_CLK)>; |
| status = "disabled"; |
| }; |
| |
| wwdg: wwdg1: watchdog@44050000 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x44050000 DT_SIZE_K(1)>; |
| clocks = <&rcc STM32_CLOCK(WWDG1, STM32_CLK)>; |
| interrupts = <8 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(64)>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
