| /* |
| * Copyright (c) 2019 Intel Corporation |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m4"; |
| reg = <0>; |
| }; |
| }; |
| |
| flash0: flash@e0000 { |
| reg = <0x000E0000 0x38000>; |
| }; |
| |
| sram0: memory@118000 { |
| compatible = "mmio-sram"; |
| reg = <0x00118000 0x8000>; |
| }; |
| |
| aliases { |
| i2c-smb-0 = &i2c_smb_0; |
| i2c-smb-1 = &i2c_smb_1; |
| i2c-smb-2 = &i2c_smb_2; |
| i2c-smb-3 = &i2c_smb_3; |
| i2c-smb-4 = &i2c_smb_4; |
| }; |
| |
| pinmux: pinmux { |
| compatible = "microchip,xec-pinmux"; |
| |
| pinmux_000_036: pinmux-0 { |
| ph-reg = <&gpio_000_036>; |
| port-num = <0>; |
| }; |
| pinmux_040_076: pinmux-1 { |
| ph-reg = <&gpio_040_076>; |
| port-num = <1>; |
| }; |
| pinmux_100_136: pinmux-2 { |
| ph-reg = <&gpio_100_136>; |
| port-num = <2>; |
| }; |
| pinmux_140_176: pinmux-3 { |
| ph-reg = <&gpio_140_176>; |
| port-num = <3>; |
| }; |
| pinmux_200_236: pinmux-4 { |
| ph-reg = <&gpio_200_236>; |
| port-num = <4>; |
| }; |
| pinmux_240_276: pinmux-5 { |
| ph-reg = <&gpio_240_276>; |
| port-num = <5>; |
| }; |
| }; |
| |
| soc { |
| pcr: pcr@40080100 { |
| reg = <0x40080100 0x100 0x4000a400 0x100>; |
| reg-names = "pcrr", "vbatr"; |
| }; |
| ecia: ecia@4000e000 { |
| reg = <0x4000e000 0x400>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| pinctrl: pin-controller@40081000 { |
| compatible = "microchip,xec-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40081000 0x1000>; |
| |
| gpio_000_036: gpio@40081000 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081000 0x80 0x40081300 0x04 |
| 0x40081380 0x04 0x400813fc 0x04>; |
| interrupts = <3 2>; |
| gpio-controller; |
| port-id = <0>; |
| girq-id = <11>; |
| #gpio-cells=<2>; |
| }; |
| gpio_040_076: gpio@40081080 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081080 0x80 0x40081304 0x04 |
| 0x40081384 0x04 0x400813f8 0x4>; |
| interrupts = <2 2>; |
| gpio-controller; |
| port-id = <1>; |
| girq-id = <10>; |
| #gpio-cells=<2>; |
| }; |
| gpio_100_136: gpio@40081100 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081100 0x80 0x40081308 0x04 |
| 0x40081388 0x04 0x400813f4 0x04>; |
| gpio-controller; |
| interrupts = <1 2>; |
| port-id = <2>; |
| girq-id = <9>; |
| #gpio-cells=<2>; |
| }; |
| gpio_140_176: gpio@40081180 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081180 0x80 0x4008130c 0x04 |
| 0x4008138c 0x04 0x400813f0 0x04>; |
| gpio-controller; |
| interrupts = <0 2>; |
| port-id = <3>; |
| girq-id = <8>; |
| #gpio-cells=<2>; |
| }; |
| gpio_200_236: gpio@40081200 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081200 0x80 0x40081310 0x04 |
| 0x40081390 0x04 0x400813ec 0x04>; |
| gpio-controller; |
| interrupts = <4 2>; |
| port-id = <4>; |
| girq-id = <12>; |
| #gpio-cells=<2>; |
| }; |
| gpio_240_276: gpio@40081280 { |
| compatible = "microchip,xec-gpio"; |
| reg = < 0x40081280 0x80 0x40081314 0x04 |
| 0x40081394 0x04 0x400813e8 0x04>; |
| gpio-controller; |
| interrupts = <17 2>; |
| port-id = <5>; |
| girq-id = <26>; |
| #gpio-cells=<2>; |
| }; |
| }; |
| rtimer: timer@40007400 { |
| compatible = "microchip,xec-rtos-timer"; |
| reg = <0x40007400 0x10>; |
| interrupts = <111 0>; |
| girqs = <23 10>; |
| }; |
| bbram: bb-ram@4000a800 { |
| compatible = "microchip,xec-bbram"; |
| reg = <0x4000a800 0x80>; |
| reg-names = "memory"; |
| }; |
| wdog: watchdog@40000400 { |
| compatible = "microchip,xec-watchdog"; |
| reg = <0x40000400 0x400>; |
| interrupts = <171 0>; |
| girqs = <21 2>; |
| pcrs = <1 9>; |
| }; |
| uart0: uart@400f2400 { |
| compatible = "ns16550"; |
| reg = <0x400f2400 0x400>; |
| interrupts = <40 0>; |
| clock-frequency = <1843200>; |
| current-speed = <38400>; |
| reg-shift = <0>; |
| status = "disabled"; |
| }; |
| uart1: uart@400f2800 { |
| compatible = "ns16550"; |
| reg = <0x400f2800 0x400>; |
| interrupts = <41 0>; |
| clock-frequency = <1843200>; |
| current-speed = <38400>; |
| reg-shift = <0>; |
| status = "disabled"; |
| }; |
| uart2: uart@400f2c00 { |
| compatible = "ns16550"; |
| reg = <0x400f2c00 0x400>; |
| interrupts = <44 0>; |
| clock-frequency = <1843200>; |
| current-speed = <38400>; |
| reg-shift = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c_smb_0: i2c@40004000 { |
| compatible = "microchip,xec-i2c"; |
| reg = <0x40004000 0x80>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <20 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| girq = <13>; |
| girq-bit = <0>; |
| }; |
| |
| i2c_smb_1: i2c@40004400 { |
| compatible = "microchip,xec-i2c"; |
| reg = <0x40004400 0x80>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <21 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| girq = <13>; |
| girq-bit = <1>; |
| }; |
| |
| i2c_smb_2: i2c@40004800 { |
| compatible = "microchip,xec-i2c"; |
| reg = <0x40004800 0x80>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <22 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| girq = <13>; |
| girq-bit = <2>; |
| }; |
| |
| i2c_smb_3: i2c@40004c00 { |
| compatible = "microchip,xec-i2c"; |
| reg = <0x40004C00 0x80>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <23 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| girq = <13>; |
| girq-bit = <3>; |
| }; |
| |
| i2c_smb_4: i2c@40005000 { |
| compatible = "microchip,xec-i2c"; |
| reg = <0x40005000 0x80>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <158 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| girq = <13>; |
| girq-bit = <4>; |
| }; |
| |
| espi0: espi@400f3400 { |
| compatible = "microchip,xec-espi"; |
| reg = <0x400f3400 0x400>; |
| interrupts = <11 3>, <15 3>, <7 3>, <16 3>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| espi_saf0: espi@40008000 { |
| compatible = "microchip,xec-espi-saf"; |
| reg = < 0x40008000 0x400 |
| 0x40070000 0x400 |
| 0x40071000 0x400>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| timer0: timer@40000c00 { |
| compatible = "microchip,xec-timer"; |
| clock-frequency = <48000000>; |
| reg = <0x40000c00 0x20>; |
| interrupts = <136 0>; |
| max-value = <0xFFFF>; |
| prescaler = <0>; |
| status = "disabled"; |
| girqs = <23 0>; |
| pcrs = <1 30>; |
| }; |
| timer1: timer@40000c20 { |
| compatible = "microchip,xec-timer"; |
| clock-frequency = <48000000>; |
| reg = <0x40000c20 0x20>; |
| interrupts = <137 0>; |
| max-value = <0xFFFF>; |
| prescaler = <0>; |
| status = "disabled"; |
| girqs = <23 1>; |
| pcrs = <1 31>; |
| }; |
| /* |
| * NOTE 1: timers 2 and 3 not implemented in MEC152x. |
| * NOTE 2: When RTOS timer used as kernel timer, timer4 used |
| * to provide high speed busy wait counter. Keep disabled to |
| * prevent counter driver from claiming it. |
| */ |
| timer4: timer@40000c80 { |
| compatible = "microchip,xec-timer"; |
| clock-frequency = <48000000>; |
| reg = <0x40000c80 0x20>; |
| interrupts = <140 0>; |
| max-value = <0xFFFFFFFF>; |
| prescaler = <0>; |
| girqs = <23 4>; |
| pcrs = <3 23>; |
| status = "disabled"; |
| }; |
| timer5: timer@40000ca0 { |
| compatible = "microchip,xec-timer"; |
| clock-frequency = <48000000>; |
| reg = <0x40000ca0 0x20>; |
| interrupts = <141 0>; |
| max-value = <0xFFFFFFFF>; |
| prescaler = <0>; |
| girqs = <23 5>; |
| pcrs = <3 24>; |
| }; |
| ps2_0: ps2@40009000 { |
| compatible = "microchip,xec-ps2"; |
| reg = <0x40009000 0x40>; |
| interrupts = <100 1>; |
| girqs = <18 10>; |
| pcrs = <3 5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| ps2_1: ps2@40009040 { |
| compatible = "microchip,xec-ps2"; |
| reg = <0x40009040 0x40>; |
| interrupts = <101 1>; |
| girqs = <18 11>; |
| pcrs = <3 6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| pwm0: pwm@40005800 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005800 0x20>; |
| pcrs = <1 4>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm1: pwm@40005810 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005810 0x20>; |
| pcrs = <1 20>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm2: pwm@40005820 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005820 0x20>; |
| pcrs = <1 21>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm3: pwm@40005830 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005830 0x20>; |
| pcrs = <1 22>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm4: pwm@40005840 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005840 0x20>; |
| pcrs = <1 23>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm5: pwm@40005850 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005850 0x20>; |
| pcrs = <1 24>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm6: pwm@40005860 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005860 0x20>; |
| pcrs = <1 25>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm7: pwm@40005870 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005870 0x20>; |
| pcrs = <1 26>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| pwm8: pwm@40005880 { |
| compatible = "microchip,xec-pwm"; |
| reg = <0x40005880 0x20>; |
| pcrs = <1 27>; |
| status = "disabled"; |
| #pwm-cells = <2>; |
| }; |
| adc0: adc@40007c00 { |
| compatible = "microchip,xec-adc"; |
| reg = <0x40007c00 0x90>; |
| interrupts = <78 0>, <79 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| clktime = <32>; |
| }; |
| kscan0: kscan@40009c00 { |
| compatible = "microchip,xec-kscan"; |
| reg = <0x40009c00 0x18>; |
| interrupts = <135 0>; |
| girqs = <21 25>; |
| pcrs = <3 11>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| peci0: peci@40006400 { |
| compatible = "microchip,xec-peci"; |
| reg = <0x40006400 0x80>; |
| interrupts = <70 4>; |
| girqs = <17 0>; |
| pcrs = <1 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| spi0: spi@40070000 { |
| compatible = "microchip,xec-qmspi"; |
| reg = <0x40070000 0x400>; |
| interrupts = <91 2>; |
| clock-frequency = <12000000>; |
| rxdma = <11>; |
| txdma = <10>; |
| lines = <1>; |
| chip_select = <0>; |
| dcsckon = <6>; |
| dckcsoff = <4>; |
| dldh = <6>; |
| dcsda = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| tach0: tach@40006000 { |
| compatible = "microchip,xec-tach"; |
| reg = <0x40006000 0x10>; |
| interrupts = <71 4>; |
| girqs = <17 1>; |
| pcrs = <1 2>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| tach1: tach@40006010 { |
| compatible = "microchip,xec-tach"; |
| reg = <0x40006010 0x10>; |
| interrupts = <72 4>; |
| girqs = <17 2>; |
| pcrs = <1 11>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| tach2: tach@40006020 { |
| compatible = "microchip,xec-tach"; |
| reg = <0x40006020 0x10>; |
| interrupts = <73 4>; |
| girqs = <17 3>; |
| pcrs = <1 12>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| tach3: tach@40006030 { |
| compatible = "microchip,xec-tach"; |
| reg = <0x40006030 0x10>; |
| interrupts = <159 4>; |
| girqs = <17 4>; |
| pcrs = <1 13>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |
| |
| &systick { |
| status = "disabled"; |
| }; |
