blob: ce7b840747bb74daf256f49aa411a3c231c0bf63 [file] [log] [blame]
/*
* Copyright 2022,2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <freq.h>
#include <arm64/armv8-a.dtsi>
#include <zephyr/dt-bindings/clock/imx_ccm.h>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/dt-bindings/rdc/imx_rdc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <3>;
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&gic>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3", "arm,gic";
reg = <0x38800000 0x10000>, /* GIC Dist */
<0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
interrupt-controller;
#interrupt-cells = <4>;
status = "okay";
};
gpt1: gpt@302d0000 {
compatible = "nxp,imx-gpt";
reg = <0x302d0000 DT_SIZE_K(64)>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
gptfreq = <24000000>;
clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>;
status = "disabled";
};
gpt2: gpt@302e0000 {
compatible = "nxp,imx-gpt";
reg = <0x302e0000 DT_SIZE_K(64)>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
gptfreq = <24000000>;
clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>;
status = "disabled";
};
iomuxc: iomuxc@30330000 {
compatible = "nxp,imx-iomuxc";
reg = <0x30330000 DT_SIZE_K(64)>;
status = "okay";
pinctrl: pinctrl {
status = "okay";
compatible = "nxp,imx8m-pinctrl";
};
};
ana_pll: ana_pll@30360000 {
compatible = "nxp,imx-ana";
reg = <0x30360000 DT_SIZE_K(64)>;
};
ccm: ccm@30380000 {
compatible = "nxp,imx-ccm";
reg = <0x30380000 DT_SIZE_K(64)>;
#clock-cells = <3>;
};
uart2: serial@30890000 {
compatible = "nxp,imx-iuart";
reg = <0x30890000 DT_SIZE_K(64)>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0";
interrupt-parent = <&gic>;
clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "nxp,imx-iuart";
reg = <0x30a60000 DT_SIZE_K(64)>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0";
interrupt-parent = <&gic>;
clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
status = "disabled";
};
rdc: rdc@303d0000 {
compatible = "nxp,rdc";
reg = <0x303d0000 DT_SIZE_K(64)>;
};
};