| * SPDX-License-Identifier: Apache-2.0 |
| * Copyright (C) 2021-2022, Intel Corporation |
| #include <zephyr/drivers/clock_control.h> |
| #include <zephyr/drivers/clock_control/clock_agilex_ll.h> |
| #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h> |
| static int clk_get_rate(const struct device *dev, |
| clock_control_subsys_t sub_system, |
| switch ((intptr_t) sub_system) { |
| case INTEL_SOCFPGA_CLOCK_MPU: |
| case INTEL_SOCFPGA_CLOCK_WDT: |
| case INTEL_SOCFPGA_CLOCK_UART: |
| case INTEL_SOCFPGA_CLOCK_MMC: |
| static DEVICE_API(clock_control, clk_api) = { |
| DEVICE_DT_DEFINE(DT_NODELABEL(clock), NULL, NULL, NULL, NULL, |
| PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, |