| /* |
| * Copyright (c) 2017, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <init.h> |
| #include <fsl_iomuxc.h> |
| |
| static int mimxrt1050_evk_init(struct device *dev) |
| { |
| ARG_UNUSED(dev); |
| |
| CLOCK_EnableClock(kCLOCK_Iomuxc); |
| CLOCK_EnableClock(kCLOCK_IomuxcSnvs); |
| |
| /* LED */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| /* SW0 */ |
| IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0); |
| |
| #ifdef CONFIG_UART_MCUX_LPUART_1 |
| /* LPUART1 TX/RX */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| return 0; |
| } |
| |
| SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0); |