boards/st/stm32f469i_disco/stm32f469i_disco.dts

/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <st/f4/stm32f469Xi.dtsi>
#include <st/f4/stm32f469nihx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
	model = "STMicroelectronics STM32F469I-DISCO board";
	compatible = "st,stm32f469i-disco";

	chosen {
		zephyr,console = &usart3;
		zephyr,shell-uart = &usart3;
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
		zephyr,ccm = &ccm0;
	};

	sdram1: sdram@c0000000 {
		compatible = "zephyr,memory-region", "mmio-sram";
		device_type = "memory";
		reg = <0xc0000000 DT_SIZE_M(16)>;
		zephyr,memory-region = "SDRAM1";
	};

	leds {
		compatible = "gpio-leds";

		green_led_1: led_1 {
			gpios = <&gpiog 6 GPIO_ACTIVE_HIGH>;
			label = "User LD1";
		};

		orange_led_2: led_2 {
			gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
			label = "User LD2";
		};

		red_led_3: led_3 {
			gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
			label = "User LD3";
		};

		blue_led_4: led_4 {
			gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
			label = "User LD4";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";

		user_button: button {
			label = "User";
			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
			zephyr,code = <INPUT_KEY_0>;
		};
	};

	aliases {
		led0 = &green_led_1;
		led1 = &orange_led_2;
		led2 = &red_led_3;
		led3 = &blue_led_4;
		sw0 = &user_button;
	};
};

&clk_lsi {
	status = "okay";
};

&clk_hse {
	clock-frequency = <DT_FREQ_M(8)>;
	status = "okay";
};

&pll {
	div-m = <8>;
	mul-n = <336>;
	div-p = <2>;
	div-q = <7>;
	clocks = <&clk_hse>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(168)>;
	ahb-prescaler = <1>;
	apb1-prescaler = <4>;
	apb2-prescaler = <2>;
};

&usart3 {
	pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&usart6 {
	pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&i2c1 {
	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
	pinctrl-names = "default";
	status = "okay";
};

&spi2 {
	pinctrl-0 = <&spi2_sck_pd3 &spi2_miso_pb14 &spi2_mosi_pb15>;
	pinctrl-names = "default";
	cs-gpios = <&gpioh 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
	status = "okay";
};

zephyr_udc0: &usbotg_fs {
	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
	pinctrl-names = "default";
	status = "okay";
};

&rtc {
	clocks = <&rcc STM32_CLOCK(APB1, 28)>,
		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
	status = "okay";
};

&sdmmc1 {
	clocks = <&rcc STM32_CLOCK(APB2, 11)>,
		 <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>;
	status = "okay";
	pinctrl-0 = <&sdio_d0_pc8
		     &sdio_d1_pc9
		     &sdio_d2_pc10
		     &sdio_d3_pc11
		     &sdio_ck_pc12
		     &sdio_cmd_pd2>;
	pinctrl-names = "default";
	cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
	disk-name = "SD";
};

&fmc {
	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
		     &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_ph2
		     &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
		     &fmc_a14_pg4 &fmc_a15_pg5
		     &fmc_d0_pd14 &fmc_d1_pd15
		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
		     &fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10
		     &fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14
		     &fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2
		     &fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9
		     &fmc_d31_pi10>;
	pinctrl-names = "default";
	status = "okay";

	sdram {
		compatible = "st,stm32-fmc-sdram";
		status = "okay";
		power-up-delay = <100>;
		num-auto-refresh = <8>;
		mode-register = <0x230>;
		/*
		 * Auto refresh command shall be issued every 15.625 us
		 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
		 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2
		 */
		refresh-rate = <1292>;

		bank@0 {
			reg = <0>;
			st,sdram-control = <STM32_FMC_SDRAM_NC_8
					    STM32_FMC_SDRAM_NR_12
					    STM32_FMC_SDRAM_MWID_32
					    STM32_FMC_SDRAM_NB_4
					    STM32_FMC_SDRAM_CAS_3
					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
					    STM32_FMC_SDRAM_RBURST_ENABLE
					    STM32_FMC_SDRAM_RPIPE_0>;
			st,sdram-timing = <2 6 4 6 2 2 2>;
		};
	};
};