| /* |
| ** ################################################################### |
| ** Processor: MKW24D512VHA5 |
| ** Compilers: Keil ARM C/C++ Compiler |
| ** Freescale C/C++ for Embedded ARM |
| ** GNU C Compiler |
| ** IAR ANSI C/C++ Compiler for ARM |
| ** MCUXpresso Compiler |
| ** |
| ** Reference manual: MKW2xDRM Rev.2 July 2014 |
| ** Version: rev. 2.0, 2014-11-26 |
| ** Build: b170112 |
| ** |
| ** Abstract: |
| ** Provides a system configuration function and a global variable that |
| ** contains the system frequency. It configures the device and initializes |
| ** the oscillator (PLL) that is part of the microcontroller device. |
| ** |
| ** Copyright (c) 2016 Freescale Semiconductor, Inc. |
| ** Copyright 2016 - 2017 NXP |
| ** Redistribution and use in source and binary forms, with or without modification, |
| ** are permitted provided that the following conditions are met: |
| ** |
| ** o Redistributions of source code must retain the above copyright notice, this list |
| ** of conditions and the following disclaimer. |
| ** |
| ** o Redistributions in binary form must reproduce the above copyright notice, this |
| ** list of conditions and the following disclaimer in the documentation and/or |
| ** other materials provided with the distribution. |
| ** |
| ** o Neither the name of the copyright holder nor the names of its |
| ** contributors may be used to endorse or promote products derived from this |
| ** software without specific prior written permission. |
| ** |
| ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ** |
| ** http: www.nxp.com |
| ** mail: support@nxp.com |
| ** |
| ** Revisions: |
| ** - rev. 1.0 (2013-11-22) |
| ** Initial version. |
| ** - rev. 2.0 (2014-11-26) |
| ** update of SystemInit() imlementation |
| ** Module access macro module_BASES replaced by module_BASE_PTRS. |
| ** Register accessor macros added to the memory map. |
| ** MCG - bit LOLS in MCG_S register renamed to LOLS0. |
| ** DAC0 registers removed. |
| ** |
| ** ################################################################### |
| */ |
| |
| /*! |
| * @file MKW24D5 |
| * @version 2.0 |
| * @date 2014-11-26 |
| * @brief Device specific configuration file for MKW24D5 (implementation file) |
| * |
| * Provides a system configuration function and a global variable that contains |
| * the system frequency. It configures the device and initializes the oscillator |
| * (PLL) that is part of the microcontroller device. |
| */ |
| |
| #include <stdint.h> |
| #include "fsl_device_registers.h" |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- ExtClk_Setup_HookUp() |
| ---------------------------------------------------------------------------- */ |
| |
| #pragma weak ExtClk_Setup_HookUp |
| uint8_t ExtClk_Setup_HookUp(uint32_t clk_out_value) { |
| uint8_t result = 0; |
| switch (clk_out_value) { |
| case 4000000U: |
| /* Start XCVR clock in order to derive MCGOUTCLK */ |
| SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ |
| GPIOB->PDDR |= 0x00080000u; /* Set PORTB.19 as output - XCVR RESET pin */ |
| GPIOC->PDDR |= 0x00000001u; /* Set PORTC.0 as output - XCVR GPIO5 pin */ |
| PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTB.19 as GPIO */ |
| PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(0x01u); /* PORTC.0 as GPIO*/ |
| GPIOC->PCOR = 0x00000001u; /* Clear XCVR GPIO5 pin*/ |
| GPIOB->PCOR = 0x00080000u; /* Clear XCVR RESET pin*/ |
| GPIOB->PSOR = 0x00080000u; /* Set XCVR RESET pin*/ |
| result = 1U; /* The output was set successfully */ |
| break; |
| case 0U: |
| /* No initialization, modem remains in the reset state */ |
| result = 1U; /* The output was set successfully */ |
| break; |
| default: |
| result = 0U; /* Requested value cannot be set */ |
| break; |
| } |
| return result; |
| } |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Core clock |
| ---------------------------------------------------------------------------- */ |
| |
| uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SystemInit() |
| ---------------------------------------------------------------------------- */ |
| |
| void SystemInit (void) { |
| /* Watchdog disable */ |
| #if (DISABLE_WDOG) |
| /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ |
| WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ |
| /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ |
| WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ |
| /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ |
| WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | |
| WDOG_STCTRLH_WAITEN_MASK | |
| WDOG_STCTRLH_STOPEN_MASK | |
| WDOG_STCTRLH_ALLOWUPDATE_MASK | |
| WDOG_STCTRLH_CLKSRC_MASK | |
| 0x0100U; |
| #endif /* (DISABLE_WDOG) */ |
| |
| } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SystemCoreClockUpdate() |
| ---------------------------------------------------------------------------- */ |
| |
| void SystemCoreClockUpdate (void) { |
| |
| uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
| uint16_t Divider; |
| |
| if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { |
| /* Output of FLL or PLL is selected */ |
| if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { |
| /* FLL is selected */ |
| if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { |
| /* External reference clock is selected */ |
| if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { |
| MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
| } else { |
| MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
| } |
| if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { |
| switch (MCG->C1 & MCG_C1_FRDIV_MASK) { |
| case 0x38U: |
| Divider = 1536U; |
| break; |
| case 0x30U: |
| Divider = 1280U; |
| break; |
| default: |
| Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
| break; |
| } |
| } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ |
| Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
| } |
| MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
| } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ |
| MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
| } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ |
| /* Select correct multiplier to calculate the MCG output clock */ |
| switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
| case 0x00U: |
| MCGOUTClock *= 640U; |
| break; |
| case 0x20U: |
| MCGOUTClock *= 1280U; |
| break; |
| case 0x40U: |
| MCGOUTClock *= 1920U; |
| break; |
| case 0x60U: |
| MCGOUTClock *= 2560U; |
| break; |
| case 0x80U: |
| MCGOUTClock *= 732U; |
| break; |
| case 0xA0U: |
| MCGOUTClock *= 1464U; |
| break; |
| case 0xC0U: |
| MCGOUTClock *= 2197U; |
| break; |
| case 0xE0U: |
| MCGOUTClock *= 2929U; |
| break; |
| default: |
| break; |
| } |
| } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ |
| /* PLL is selected */ |
| Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); |
| MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ |
| Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); |
| MCGOUTClock *= Divider; /* Calculate the MCG output clock */ |
| } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ |
| } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { |
| /* Internal reference clock is selected */ |
| if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { |
| MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
| } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ |
| Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); |
| MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ |
| } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ |
| } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { |
| /* External reference clock is selected */ |
| if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { |
| MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
| } else { |
| MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
| } |
| } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ |
| /* Reserved value */ |
| return; |
| } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ |
| SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
| } |