| /* |
| * Copyright (c) 2024 Nordic Semiconductor ASA |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /dts-v1/; |
| #include <nordic/nrf54l15_cpuapp.dtsi> |
| #include "nrf54l15pdk_nrf54l15-common.dtsi" |
| |
| / { |
| compatible = "nordic,nrf54l15pdk_nrf54l15-cpuapp"; |
| model = "Nordic nRF54L15 PDK nRF54L15 Application MCU"; |
| |
| chosen { |
| zephyr,console = &uart20; |
| zephyr,shell-uart = &uart20; |
| zephyr,uart-mcumgr = &uart20; |
| zephyr,flash-controller = &rram_controller; |
| zephyr,flash = &cpuapp_rram; |
| zephyr,code-partition = &slot0_partition; |
| zephyr,sram = &cpuapp_sram; |
| zephyr,ieee802154 = &ieee802154; |
| }; |
| |
| aliases { |
| spi-flash0 = &mx25r64; |
| }; |
| }; |
| |
| &cpuapp_sram { |
| status = "okay"; |
| }; |
| |
| &lfxo { |
| load-capacitors = "internal"; |
| load-capacitance-femtofarad = <15500>; |
| }; |
| |
| &hfxo { |
| load-capacitors = "internal"; |
| load-capacitance-femtofarad = <15000>; |
| }; |
| |
| &grtc { |
| owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; |
| /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ |
| child-owned-channels = <3 4 7 8 9 10 11>; |
| status = "okay"; |
| }; |
| |
| &cpuapp_rram { |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| boot_partition: partition@0 { |
| label = "mcuboot"; |
| reg = <0x0 DT_SIZE_K(64)>; |
| }; |
| slot0_partition: partition@10000 { |
| label = "image-0"; |
| reg = <0x10000 DT_SIZE_K(324)>; |
| }; |
| slot0_ns_partition: partition@61000 { |
| label = "image-0-nonsecure"; |
| reg = <0x61000 DT_SIZE_K(324)>; |
| }; |
| slot1_partition: partition@b2000 { |
| label = "image-1"; |
| reg = <0xb2000 DT_SIZE_K(324)>; |
| }; |
| slot1_ns_partition: partition@103000 { |
| label = "image-1-nonsecure"; |
| reg = <0x103000 DT_SIZE_K(324)>; |
| }; |
| /* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */ |
| storage_partition: partition@15c000 { |
| label = "storage"; |
| reg = <0x15c000 DT_SIZE_K(36)>; |
| }; |
| }; |
| }; |
| |
| &uart20 { |
| status = "okay"; |
| hw-flow-control; |
| }; |
| |
| &gpio0 { |
| status = "okay"; |
| }; |
| |
| &gpio1 { |
| status = "okay"; |
| }; |
| |
| &gpio2 { |
| status = "okay"; |
| }; |
| |
| &gpiote20 { |
| status = "okay"; |
| }; |
| |
| &gpiote30 { |
| status = "okay"; |
| }; |
| |
| &radio { |
| status = "okay"; |
| }; |
| |
| &ieee802154 { |
| status = "okay"; |
| }; |
| |
| &temp { |
| status = "okay"; |
| }; |
| |
| &clock { |
| status = "okay"; |
| }; |
| |
| &spi00 { |
| status = "okay"; |
| cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; |
| pinctrl-0 = <&spi00_default>; |
| pinctrl-1 = <&spi00_sleep>; |
| pinctrl-names = "default", "sleep"; |
| |
| mx25r64: mx25r6435f@0 { |
| compatible = "jedec,spi-nor"; |
| status = "disabled"; |
| reg = <0>; |
| spi-max-frequency = <8000000>; |
| jedec-id = [c2 28 17]; |
| sfdp-bfp = [ |
| e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb |
| ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 |
| 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44 |
| 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff |
| ]; |
| size = <67108864>; |
| has-dpd; |
| t-enter-dpd = <10000>; |
| t-exit-dpd = <35000>; |
| }; |
| }; |