boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts

/*
 * Copyright (c) 2024 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <nordic/nrf54l15_cpuflpr.dtsi>
#include "nrf54l15pdk_nrf54l15-common.dtsi"

/ {
	model = "Nordic nRF54L15 PDK nRF54L15 FLPR MCU";
	compatible = "nordic,nrf54l15pdk_nrf54l15-cpuflpr";

	chosen {
		zephyr,console = &uart30;
		zephyr,shell-uart = &uart30;
		zephyr,code-partition = &cpuflpr_code_partition;
		zephyr,flash = &cpuflpr_rram;
		zephyr,sram = &cpuflpr_sram;
	};
};

&cpuflpr_sram {
	status = "okay";
	/* size must be increased due to booting from SRAM */
	reg = <0x20028000 DT_SIZE_K(96)>;
	ranges = <0x0 0x20028000 0x18000>;
};

&cpuflpr_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		cpuflpr_code_partition: partition@0 {
			label = "image-0";
			reg = <0x0 DT_SIZE_K(96)>;
		};
	};
};

&grtc {
	owned-channels = <3 4>;
	status = "okay";
};

&uart30 {
	status = "okay";
	hw-flow-control;
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpiote20 {
	status = "okay";
};

&gpiote30 {
	status = "okay";
};