| # Copyright 2024 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_SERIES_MCXN |
| select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE |
| select CLOCK_CONTROL |
| select ARM |
| select HAS_MCUX |
| select HAS_MCUX_FLEXCOMM |
| select CPU_CORTEX_M_HAS_SYSTICK |
| select CPU_CORTEX_M_HAS_DWT |
| select SOC_RESET_HOOK |
| |
| config SOC_MCXN947_CPU0 |
| select CPU_CORTEX_M33 |
| select CPU_HAS_ARM_SAU |
| select CPU_HAS_ARM_MPU |
| select CPU_HAS_FPU |
| select ARMV8_M_DSP |
| select ARM_TRUSTZONE_M |
| select HAS_MCUX_CACHE |
| |
| config SOC_MCXN236 |
| select CPU_CORTEX_M33 |
| select CPU_HAS_ARM_SAU |
| select CPU_HAS_ARM_MPU |
| select CPU_HAS_FPU |
| select ARMV8_M_DSP |
| select ARM_TRUSTZONE_M |
| select HAS_MCUX_CACHE |
| |
| if SOC_SERIES_MCXN |
| |
| if SOC_MCXN947 |
| config SECOND_CORE_MCUX |
| bool "MCXN94X's second core" |
| depends on HAS_MCUX |
| help |
| Indicates the second core will be enabled, and the part will run |
| in dual core mode. |
| |
| config FLASH_DISABLE_CACHE64 |
| bool "Disable the CACHE64 cache for FlexSPI flash accesses" |
| help |
| Disable cache64 cache. |
| |
| config MCUX_CORE_SUFFIX |
| default "_cm33_core0" if SOC_MCXN947_CPU0 |
| default "_cm33_core1" if SOC_MCXN947_CPU1 |
| endif |
| |
| rsource "../../common/Kconfig.flexspi_xip" |
| |
| endif # SOC_SERIES_MCXN |
