blob: 0931a27b0cc45574ac230deefd137c7be312f846 [file] [log] [blame]
# Copyright (c) 2018 Foundries.io Ltd
# SPDX-License-Identifier: Apache-2.0
config SOC_OPENISA_RV32M1_RISCV32
bool "OpenISA RV32M1 RISC-V cores"
select RISCV
# The following select is due to limitations in the linker script.
# (We can't make it a 'depends on' without causing a dependency loop).
select XIP
select HAS_RV32M1_LPUART
select HAS_RV32M1_LPI2C
select HAS_RV32M1_LPSPI
select HAS_RV32M1_TPM
select ATOMIC_OPERATIONS_C
select VEGA_SDK_HAL
select RISCV_SOC_INTERRUPT_INIT
select CLOCK_CONTROL
select HAS_RV32M1_FTFX
select HAS_FLASH_LOAD_OFFSET
select BUILD_OUTPUT_HEX
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
help
Enable support for OpenISA RV32M1 RISC-V processors. Choose
this option to target the RI5CY or ZERO-RISCY core. This
option should not be used to target either Arm core.