| # Copyright (c) 2022 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| description: | |
| The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These |
| nodes can be autogenerated using the MCUXpresso config tools combined with |
| the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg |
| fields in a group select the pins to be configured, and the remaining |
| devicetree properties set configuration values for those pins |
| for example, here is an group configuring LPUART1 pins: |
| |
| group0 { |
| pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx:, |
| &iomuxc_uart4_txd_uart_tx_uart4_tx>; |
| bias-pull-up; |
| slew-rate = "slow"; |
| drive-strength = "x1"; |
| }; |
| |
| This will select UART4_RXD as UART4 rx, and UART4_TXD as UART4 tx. |
| Both pins will be configured with a slow slew rate, and minimum drive |
| strength. |
| Note that the soc level iomuxc dts file can be examined to find the possible |
| pinmux options. Here are the affects of each property on the |
| IOMUXC SW_PAD_CTL register: |
| input-schmitt-enable: HYS=1 |
| bias-pull-up: PUE=1, PE=1 |
| bias-pull-down: PUE=0, PE=1 |
| drive-open-drain: ODE=1 |
| slew-rate: FSEL=<enum_idx> |
| drive-strength: DSE=<enum_idx> |
| input-enable: SION=1 (in SW_MUX_CTL_PAD register) |
| |
| If only required properties are supplied, the pin will have the following |
| configuration: |
| HYS=0, |
| PE=0 |
| PUE=0 |
| ODE=0, |
| SRE=<slew-rate>, |
| DSE=<drive-strength>, |
| SION=0, |
| |
| |
| compatible: "nxp,imx8mp-pinctrl" |
| |
| include: |
| - name: base.yaml |
| - name: pincfg-node-group.yaml |
| child-binding: |
| child-binding: |
| property-allowlist: |
| - input-schmitt-enable |
| - drive-open-drain |
| - input-enable |
| - bias-pull-up |
| - bias-pull-down |
| |
| child-binding: |
| description: iMX pin controller pin group |
| child-binding: |
| description: | |
| iMX pin controller pin configuration node. |
| properties: |
| pinmux: |
| required: true |
| type: phandles |
| description: | |
| Pin mux selections for this group. See the soc level iomuxc DTSI file |
| for a defined list of these options. |
| drive-strength: |
| required: true |
| type: string |
| enum: |
| - "x1" |
| - "x4" |
| - "x2" |
| - "x6" |
| description: | |
| Pin output drive strength. Sets the DSE field in the IOMUXC peripheral. |
| 00 X1- low drive strength |
| 01 X4- high drive strength |
| 10 X2- medium drive strength |
| 11 X6- max drive strength |
| slew-rate: |
| required: true |
| type: string |
| enum: |
| - "slow" |
| - "fast" |
| description: | |
| Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral |
| 0 SLOW — Slow Frequency Slew Rate |
| 1 FAST — Fast Frequency Slew Rate |
