| # Copyright 2021 The Chromium OS Authors |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| description: | |
| ST STM32 family USB Type-C / Power Delivery. The default values were |
| taken from the LL_UCPD_StructInit function defined in the HAL. |
| |
| compatible: "st,stm32-ucpd" |
| |
| include: base.yaml |
| |
| properties: |
| label: |
| required: true |
| |
| reg: |
| required: true |
| |
| clocks: |
| required: true |
| |
| interrupts: |
| required: true |
| |
| psc-ucpdclk: |
| required: false |
| default: 2 |
| type: int |
| enum: |
| - 1 |
| - 2 |
| - 4 |
| - 8 |
| - 16 |
| - 32 |
| - 64 |
| - 128 |
| description: | |
| Determines the division ratio of a kernel clock pre-scaler |
| producing UCPD peripheral clock (ucpd_clk). It is recommended |
| to use the pre-scaler so as to set the ucpd_clk frequency in |
| the range from 6 to 9 MHz. |
| |
| ifrgap: |
| required: false |
| type: int |
| default: 17 |
| description: | |
| Determines the division ratio of a ucpd_clk divider producing |
| inter-frame gap timer clock (tInterFrameGap). |
| The division ratio 15 is to apply for Tx clock at the USB PD 2.0 |
| specification nominal value. |
| Valid range: 2 - 32 |
| |
| transwin: |
| required: false |
| type: int |
| default: 8 |
| description: | |
| Determines the division ratio of a hbit_clk divider producing |
| tTransitionWindow interval. |
| Valid range: 2 - 32 |
| |
| hbitclkdiv: |
| required: false |
| type: int |
| default: 14 |
| description: | |
| Determines the division ratio of a ucpd_clk divider producing |
| half-bit clock (hbit_clk) |
| Valid range: 1 - 64 |