| # LPC LPC54XXX MCU line |
| |
| # Copyright (c) 2017, NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| choice |
| prompt "LPC LPC54XXX MCU Selection" |
| depends on SOC_SERIES_LPC54XXX |
| |
| config SOC_LPC54114_M4 |
| bool "SOC_LPC54114_M4" |
| select CPU_CORTEX_M4 |
| select CPU_CORTEX_M_HAS_DWT |
| select CPU_HAS_ARM_MPU |
| select PLATFORM_SPECIFIC_INIT |
| select CLOCK_CONTROL |
| select HAS_MCUX_IAP_LEGACY |
| |
| config SOC_LPC54114_M0 |
| bool "SOC_LPC54114_M0" |
| select CPU_CORTEX_M0PLUS |
| select CPU_CORTEX_M_HAS_VTOR |
| select CLOCK_CONTROL |
| |
| endchoice |
| |
| if SOC_SERIES_LPC54XXX |
| |
| config SOC_PART_NUMBER_LPC54114J256BD64 |
| bool |
| |
| config SOC_PART_NUMBER_LPC54XXX |
| string |
| default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64 |
| |
| help |
| This string holds the full part number of the SoC. It is a hidden |
| option that you should not set directly. The part number selection |
| choice defines the default value for this string. |
| |
| config SECOND_CORE_MCUX |
| bool "LPC54114 Cortex-M0 second core" |
| depends on HAS_MCUX |
| help |
| Driver for second core startup |
| |
| config SECOND_CORE_BOOT_ADDRESS_MCUX |
| depends on SECOND_CORE_MCUX |
| hex "Address the second core will boot at" |
| default 0x20010000 |
| help |
| This is the address the second core will boot from. Additionally this |
| address is where we will copy the SECOND_IMAGE to. We default this to |
| the base of SRAM1. |
| |
| # Workaround for not being able to have commas in macro arguments |
| DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition |
| |
| # Move the LMA address of second core into flash |
| config BUILD_OUTPUT_ADJUST_LMA |
| depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 |
| default "-0x20010000+\ |
| $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" |
| |
| config BUILD_OUTPUT_INFO_HEADER |
| default y |
| depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 |
| |
| endif # SOC_SERIES_LPC54XXX |
