| /* |
| * Copyright (c) 2021, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <nxp/nxp_rt11xx.dtsi> |
| |
| / { |
| cpus { |
| /delete-node/ cpu@0; |
| }; |
| |
| /* |
| * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected |
| * to the M4 core alone, hence this EDMA controller has been designated M4 only. |
| * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are |
| * only accesssible to the M4. |
| * |
| * Refer to Chapter 3 of the Reference Manual |
| */ |
| soc { |
| /delete-node/ dma-controller@40070000; |
| |
| sram0: memory@1ffe0000 { |
| compatible = "mmio-sram"; |
| reg = <0x1ffe0000 DT_SIZE_K(128)>; |
| }; |
| |
| sram1: memory@20000000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(128)>; |
| zephyr,memory-region = "SRAM1"; |
| }; |
| |
| /* |
| * M4 uses different addresses from the M7 core for GPIO2 and |
| * GPIO3, see pg. 1410 of RT1170 ref manual for example |
| */ |
| gpio2: gpio@40130000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x40130000 0x4000>; |
| interrupts = <102 0>, <103 0>; |
| label = "GPIO_2"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio3: gpio@40134000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x40134000 0x4000>; |
| interrupts = <104 0>, <105 0>; |
| label = "GPIO_3"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| sai1: sai@40404000 { |
| dmas = <&edma_lpsr0 0 54>, <&edma_lpsr0 0 55>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <0>; |
| nxp,rx-dma-channel = <1>; |
| }; |
| |
| sai2: sai@40408000 { |
| dmas = <&edma_lpsr0 0 56>, <&edma_lpsr0 0 57>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <3>; |
| nxp,rx-dma-channel = <4>; |
| }; |
| |
| sai3: sai@4040c000 { |
| dmas = <&edma_lpsr0 0 58>, <&edma_lpsr0 0 59>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <5>; |
| nxp,rx-dma-channel = <6>; |
| }; |
| |
| sai4: sai@40c40000 { |
| dmas = <&edma_lpsr0 0 60>, <&edma_lpsr0 0 61>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <7>; |
| nxp,rx-dma-channel = <8>; |
| }; |
| }; |
| }; |
| |
| &gpio9 { |
| interrupts = <99 0>; |
| }; |
| |
| &gpio11 { |
| /* GPIO 7-11 share the same interrupt on the CM4 */ |
| interrupts = <99 0>; |
| status = "disabled"; |
| }; |
| |
| /* Set default power states for CM4 cpu */ |
| &cpu1 { |
| cpu-power-states = <&idle &suspend>; |
| }; |