blob: 71b23edd600e1b854cf0242c9f0e8364e9360282 [file] [log] [blame]
/*
* Copyright (c) 2021, Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
#include <zephyr/dt-bindings/reset/gd32f4xx.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(112)>;
};
rcu: reset-clock-controller@40023800 {
compatible = "gd,gd32-rcu";
reg = <0x40023800 0x400>;
status = "okay";
cctl: clock-controller {
compatible = "gd,gd32-cctl";
#clock-cells = <1>;
status = "okay";
};
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40023c00 {
compatible = "gd,gd32-flash-controller";
reg = <0x40023c00 0x400>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "gd,gd32-nv-flash-v3", "soc-nv-flash";
write-block-size = <2>;
max-erase-time-ms = <8000>;
};
};
usart0: usart@40011000 {
compatible = "gd,gd32-usart";
reg = <0x40011000 0x400>;
interrupts = <37 0>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
usart1: usart@40004400 {
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
usart2: usart@40004800 {
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
uart3: usart@40004c00 {
compatible = "gd,gd32-usart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
clocks = <&cctl GD32_CLOCK_UART3>;
resets = <&rctl GD32_RESET_UART3>;
status = "disabled";
};
uart4: usart@40005000 {
compatible = "gd,gd32-usart";
reg = <0x40005000 0x400>;
interrupts = <52 0>;
clocks = <&cctl GD32_CLOCK_UART4>;
resets = <&rctl GD32_RESET_UART4>;
status = "disabled";
};
usart5: usart@40011400 {
compatible = "gd,gd32-usart";
reg = <0x40011400 0x400>;
interrupts = <71 0>;
clocks = <&cctl GD32_CLOCK_USART5>;
resets = <&rctl GD32_RESET_USART5>;
status = "disabled";
};
uart6: usart@40007800 {
compatible = "gd,gd32-usart";
reg = <0x40007800 0x400>;
interrupts = <82 0>;
clocks = <&cctl GD32_CLOCK_UART6>;
resets = <&rctl GD32_RESET_UART6>;
status = "disabled";
};
uart7: usart@40007c00 {
compatible = "gd,gd32-usart";
reg = <0x40007c00 0x400>;
interrupts = <83 0>;
clocks = <&cctl GD32_CLOCK_UART7>;
resets = <&rctl GD32_RESET_UART7>;
status = "disabled";
};
dac: dac@40007400 {
compatible = "gd,gd32-dac";
reg = <0x40007400 0x400>;
clocks = <&cctl GD32_CLOCK_DAC>;
resets = <&rctl GD32_RESET_DAC>;
num-channels = <2>;
status = "disabled";
#io-channel-cells = <1>;
};
i2c0: i2c@40005400 {
compatible = "gd,gd32-i2c";
reg = <0x40005400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
clocks = <&cctl GD32_CLOCK_I2C0>;
resets = <&rctl GD32_RESET_I2C0>;
status = "disabled";
};
i2c1: i2c@40005800 {
compatible = "gd,gd32-i2c";
reg = <0x40005800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
clocks = <&cctl GD32_CLOCK_I2C1>;
resets = <&rctl GD32_RESET_I2C1>;
status = "disabled";
};
i2c2: i2c@40005c00 {
compatible = "gd,gd32-i2c";
reg = <0x40005c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
clocks = <&cctl GD32_CLOCK_I2C2>;
resets = <&rctl GD32_RESET_I2C2>;
status = "disabled";
};
spi0: spi@40013000 {
compatible = "gd,gd32-spi";
reg = <0x40013000 0x400>;
interrupts = <35 0>;
clocks = <&cctl GD32_CLOCK_SPI0>;
resets = <&rctl GD32_RESET_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@40003800 {
compatible = "gd,gd32-spi";
reg = <0x40003800 0x400>;
interrupts = <36 0>;
clocks = <&cctl GD32_CLOCK_SPI1>;
resets = <&rctl GD32_RESET_SPI1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi2: spi@40003c00 {
compatible = "gd,gd32-spi";
reg = <0x40003c00 0x400>;
interrupts = <51 0>;
clocks = <&cctl GD32_CLOCK_SPI2>;
resets = <&rctl GD32_RESET_SPI2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
adc0: adc@40012000 {
compatible = "gd,gd32-adc";
reg = <0x40012000 0x100>;
interrupts = <18 0>;
clocks = <&cctl GD32_CLOCK_ADC0>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
adc1: adc@40012100 {
compatible = "gd,gd32-adc";
reg = <0x40012100 0x100>;
interrupts = <18 0>;
clocks = <&cctl GD32_CLOCK_ADC1>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
adc2: adc@40012200 {
compatible = "gd,gd32-adc";
reg = <0x40012200 0x100>;
interrupts = <18 0>;
clocks = <&cctl GD32_CLOCK_ADC2>;
resets = <&rctl GD32_RESET_ADC2>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
syscfg: syscfg@40013800 {
compatible = "gd,gd32-syscfg";
reg = <0x40013800 0x400>;
clocks = <&cctl GD32_CLOCK_SYSCFG>;
};
exti: interrupt-controller@40013c00 {
compatible = "gd,gd32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40013c00 0x400>;
num-lines = <23>;
interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
<40 0>;
interrupt-names = "line0", "line1", "line2", "line3",
"line4", "line5-9", "line10-15";
status = "okay";
};
pinctrl: pin-controller@40020000 {
compatible = "gd,gd32-pinctrl-af";
reg = <0x40020000 0x2400>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
gpioa: gpio@40020000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOA>;
resets = <&rctl GD32_RESET_GPIOA>;
status = "disabled";
};
gpiob: gpio@40020400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOB>;
resets = <&rctl GD32_RESET_GPIOB>;
status = "disabled";
};
gpioc: gpio@40020800 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020800 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOC>;
resets = <&rctl GD32_RESET_GPIOC>;
status = "disabled";
};
gpiod: gpio@40020c00 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020c00 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOD>;
resets = <&rctl GD32_RESET_GPIOD>;
status = "disabled";
};
gpioe: gpio@40021000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021000 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOE>;
resets = <&rctl GD32_RESET_GPIOE>;
status = "disabled";
};
gpiof: gpio@40021400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOF>;
resets = <&rctl GD32_RESET_GPIOF>;
status = "disabled";
};
gpiog: gpio@40021800 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOG>;
resets = <&rctl GD32_RESET_GPIOG>;
status = "disabled";
};
gpioh: gpio@40021c00 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021c00 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOH>;
resets = <&rctl GD32_RESET_GPIOH>;
status = "disabled";
};
gpioi: gpio@40022000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022000 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOI>;
resets = <&rctl GD32_RESET_GPIOI>;
status = "disabled";
};
};
timer0: timer@40010000 {
compatible = "gd,gd32-timer";
reg = <0x40010000 0x400>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
clocks = <&cctl GD32_CLOCK_TIMER0>;
resets = <&rctl GD32_RESET_TIMER0>;
is-advanced;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer1: timer@40000000 {
compatible = "gd,gd32-timer";
reg = <0x40000000 0x400>;
interrupts = <28 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER1>;
resets = <&rctl GD32_RESET_TIMER1>;
is-32bit;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer2: timer@40000400 {
compatible = "gd,gd32-timer";
reg = <0x40000400 0x400>;
interrupts = <29 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER2>;
resets = <&rctl GD32_RESET_TIMER2>;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer3: timer@40000800 {
compatible = "gd,gd32-timer";
reg = <0x40000800 0x400>;
interrupts = <30 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER3>;
resets = <&rctl GD32_RESET_TIMER3>;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer4: timer@40000c00 {
compatible = "gd,gd32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER4>;
resets = <&rctl GD32_RESET_TIMER4>;
is-32bit;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer5: timer@40001000 {
compatible = "gd,gd32-timer";
reg = <0x40001000 0x400>;
interrupts = <54 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER5>;
resets = <&rctl GD32_RESET_TIMER5>;
channels = <0>;
status = "disabled";
};
timer6: timer@40001400 {
compatible = "gd,gd32-timer";
reg = <0x40001400 0x400>;
interrupts = <55 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER6>;
resets = <&rctl GD32_RESET_TIMER6>;
channels = <0>;
status = "disabled";
};
timer7: timer@40010400 {
compatible = "gd,gd32-timer";
reg = <0x40010400 0x400>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
clocks = <&cctl GD32_CLOCK_TIMER7>;
resets = <&rctl GD32_RESET_TIMER7>;
is-advanced;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer8: timer@40014000 {
compatible = "gd,gd32-timer";
reg = <0x40014000 0x400>;
interrupts = <24 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER8>;
resets = <&rctl GD32_RESET_TIMER8>;
channels = <2>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer9: timer@40014400 {
compatible = "gd,gd32-timer";
reg = <0x40014400 0x400>;
interrupts = <25 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER9>;
resets = <&rctl GD32_RESET_TIMER9>;
channels = <1>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer10: timer@40014800 {
compatible = "gd,gd32-timer";
reg = <0x40014800 0x400>;
interrupts = <26 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER10>;
resets = <&rctl GD32_RESET_TIMER10>;
channels = <1>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer11: timer@40001800 {
compatible = "gd,gd32-timer";
reg = <0x40001800 0x400>;
interrupts = <43 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER11>;
resets = <&rctl GD32_RESET_TIMER11>;
channels = <2>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer12: timer@40001c00 {
compatible = "gd,gd32-timer";
reg = <0x40001c00 0x400>;
interrupts = <44 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER12>;
resets = <&rctl GD32_RESET_TIMER12>;
channels = <1>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer13: timer@40002000 {
compatible = "gd,gd32-timer";
reg = <0x40002000 0x400>;
interrupts = <45 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER13>;
resets = <&rctl GD32_RESET_TIMER13>;
channels = <1>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
dma0: dma@40026000 {
compatible = "gd,gd32-dma";
reg = <0x40026000 0x400>;
interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
<15 0>, <16 0>, <17 0>, <47 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
resets = <&rctl GD32_RESET_DMA0>;
dma-channels = <8>;
#dma-cells = <1>;
status = "disabled";
};
dma1: dma@40026400 {
compatible = "gd,gd32-dma";
reg = <0x40026400 0x400>;
interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
<60 0>, <68 0>, <69 0>, <70 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
resets = <&rctl GD32_RESET_DMA1>;
dma-channels = <8>;
#dma-cells = <1>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};