| /* |
| * Copyright (c) 2024-2025 Analog Devices, Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <arm/armv8-m.dtsi> |
| #include <zephyr/dt-bindings/clock/adi_max32_clock.h> |
| |
| / { |
| soc { |
| sram: sram@20000000 { |
| ranges = <0x0 0x20000000 0x40000>; |
| }; |
| |
| peripheral: peripheral@40000000 { |
| ranges = <0x0 0x40000000 0x10000000>; |
| |
| pinctrl: pin-controller@8000 { |
| ranges = <0x8000 0x40008000 0x1000>; |
| }; |
| |
| dma0: dma@28000 { |
| compatible = "adi,max32-dma"; |
| reg = <0x28000 0x1000>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>; |
| interrupts = <16 0>, <17 0>, <18 0>, <19 0>; |
| dma-channels = <4>; |
| status = "disabled"; |
| #dma-cells = <2>; |
| }; |
| }; |
| |
| flc0: flash_controller@50029000 { |
| compatible = "adi,max32-flash-controller"; |
| reg = <0x50029000 0x400>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "okay"; |
| |
| flash0: flash@1000000 { |
| compatible = "soc-nv-flash"; |
| reg = <0x01000000 DT_SIZE_K(1024)>; |
| write-block-size = <16>; |
| erase-block-size = <8192>; |
| }; |
| }; |
| }; |
| }; |
| |
| #include "max32657_common.dtsi" |
