dts/bindings/flash_controller/st,stm32-qspi-nor.yaml

# Copyright (c) 2020, Linaro limited
# SPDX-License-Identifier: Apache-2.0

description: |
    STM32 QSPI Flash controller supporting the JEDEC CFI interface

    Representation of a serial flash on a quadspi bus:

        mx25r6435f: qspi-nor-flash@0 {
                compatible = "st,stm32-qspi-nor";
                reg = <0>;
                size = <DT_SIZE_M(64)>; /* 64 Mbits */
                qspi-max-frequency = <80000000>;
                reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
                reset-gpios-duration = <1>;
                spi-bus-width = <4>;
                status = "okay";
        };

compatible: "st,stm32-qspi-nor"

include: ["flash-controller.yaml", "jedec,jesd216.yaml"]

on-bus: qspi

properties:
  size:
    required: true
    description: Flash Memory size in bits
  reg:
    required: true
    description: Flash Memory base address and size in bytes
  qspi-max-frequency:
    type: int
    required: true
    description: Maximum clock frequency of device's QSPI interface in Hz
  reset-gpios:
    type: phandle-array
    description: RESETn pin
  reset-gpios-duration:
    type: int
    description: The duration (in ms) for the flash memory reset pulse
  reset-cmd:
    type: boolean
    description: Send reset command on initialization
  reset-cmd-wait:
    type: int
    default: 10
    description: The duration (in us) to wait after reset command
  spi-bus-width:
    type: int
    description: The width of (Q)SPI bus to which flash memory is connected.
                 Now only value of 4 (when using SIO[0123]) is supported.
  writeoc:
    type: string
    enum:
      - "PP_1_1_4"      # Quad data line SPI, PP 1-1-4 (0x32)
      - "PP_1_4_4"      # Quad data line SPI, PP 1-4-4 (0x38)
    description: |
      The value encodes number of I/O lines used for the opcode,
      address, and data.

      There is no info about quad page program opcodes in the SFDP
      tables, hence it has been assumed that NOR flash memory
      supporting 1-4-4 mode also would support fast page programming.

      If absent, then 1-4-4 program page is used in quad mode.

  requires-ulbpr:
    type: boolean
    description: |
      Indicates the device requires the ULBPR (0x98) command.

      Some flash chips such as the Microchip SST26VF series have a block
      protection register that initializes to write-protected.  Use this
      property to indicate that the BPR must be unlocked before write
      operations can proceed.

  st,read-id-dummy-cycles:
    type: int
    default: 8
    description: The number of dummy-cycles required when reading jedec id

  cs-high-time:
    type: int
    default: 8
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
    description: |
      Minimum number of QSPI clock cycles the chip select signal must remain
      high between commands issued to the flash memory.

      The minimum acceptable value depends on the flash memory model and the
      QSPI clock frequency. Using a value higher than the minimum required
      by the flash memory would not lead to communication errors but is
      suboptimal as it would reduce the throughput.

      Defaults to 8 clock cycles, which is the maximum supported value.