tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/clear_clocks.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay clears clocks back to a state equivalent to what could
 * be found in stm32u5.dtsi
 */

&clk_hse {
	status = "disabled";
	/delete-property/ clock-frequency;
	/delete-property/ hse-bypass;
};

&clk_hsi {
	status = "disabled";
};

&clk_lse {
	status = "disabled";
};

&clk_msis {
	status = "disabled";
	/delete-property/ msi-range;
	/delete-property/ msi-pll-mode;
};

&pll1 {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&rcc {
	/delete-property/ clocks;
	/delete-property/ clock-frequency;
	/delete-property/ ahb-prescaler;
	/delete-property/ apb1-prescaler;
	/delete-property/ apb2-prescaler;
	/delete-property/ apb3-prescaler;
};